Topics:
Processor:
  basics (Chapter 1 and 2 of P&H),
  instruction-set of modern processors (Chapter 3 of P&H),
  implementation techniques (Chapter 5 of P&H),
  buses, interrupts, traps, exceptions,
  pipelining and superscalar design (Chapter 6.1 and 6.2 of P&H)
  and processor performance (Chapter 2 of P&H).

Process abstraction:
  process, address space, process states (Chapters 4.1, 4.2,
  4.3 of S&G);
  context switch, CPU scheduling, multiprogramming, timesharing
  (Ch 5 of S&G except 5.4 and 5.5)

Memory Management (Chapters 8 and 9 of S&G; Chapter 7.4 of P&H):
  hardware and software (evolution and state-of-the art)
  for memory allocation,
  address translation, paging, segmentation,
  concept of virtual memory,
  memory protection, page faults, memory mapping,
  free space management, page replacement algorithms,
  translation lookaside buffer, memory management unit,
  VM management policies, working sets.

Memory hierarchy (Chapter 7.1 and 7.2 of P&H):
  cache memory organization,
  L1 and L2 caches, and interface to processor,