From kenmac Thu Sep 28 16:36:45 -0400 2000
From: "Kenneth M. Mackenzie" <kenmac@midway.cc.gatech.edu>
To: gte220x@prism, gte584f@prism, gt4947c@prism, gt8230b@prism, gte225u@prism, gte211q@prism, gte020r@prism, gte534w@prism, gte572q@prism, gte463q@prism, gt9182b@prism, gt0178f@prism, gt6645f@prism, gte823q@prism, gte148r@prism, gte909q@prism, gt5231a@prism, gte930q@prism, gte829m@prism, gte163i@prism, gt5193d@prism, gte182g@prism, gt7150b@prism, gte409s@prism, gte161h@prism, gt5809a@prism, gt6671b@prism, gt7116c@prism
CC: pp, ronp
In-reply-to: <200009281229.IAA25762@gaia.cc.gatech.edu> (ronp@cc.gatech.edu)
Subject: Re: Question on jumps
Reply-to: kenmac@cc.gatech.edu
References:  <200009281229.IAA25762@gaia.cc.gatech.edu>

Hi all,

Ron writes:
> Regarding question 1 and when the next loop starts after a branch.
> When I talked to Pat on Monday, she said it was after the decode
> section where the zero comariter is? Yesterday, Mackenzie said it's
> after the exicute phase. Who is right and why?  Ron

Okay, I'll accept answers of 1, 2 or 3 stall cycles on a branch for
parts a/b on homework 3.  Just tell me what you did.  Take your pick:

2. I said 2 stall cycles in class, corresponding to the branch
   being resolved in the EX stage.  I can't find anyone to agree with
   me on this, not even my lecture slides... :-(

3. The book starts out (in Section 3.5) with 3 cycle stalls,
   corresponding to resolving the branch in the MEM stage.

     --> Fig 3.4 in the text (or in Wednesday's slides) shows this circuit
     --> Fig 3.21 in the text shows the timing diagram with three stalls
     --> The "control hazard" slide in Monday's lecture shows a
         three-cycle stall.
     --> The super-secret solution guide to the book (I don't
         ordinarily look at this) (it has bugs, too) assumes a
         three-cycle stall for parts a/b

1. The book also develops a circuit with 1 cycle stalls, corresponding
   to resolving the branch in the ID stage

     --> Fig 3.22 in the text shows this circuit -- actually there's a
         subtle bug in this circuit in the book, the fix is in
         Monday's lecture slides
     --> Fig 3.26 in the text shows the timing digram with one stall
     --> There's a nice symmetry here with the one-cycle delay slot.
         The datapath is the same whether it's a delay slot or a
         stall, it's just the pipeline control logic that determines
         whether the second cycle is exposed or not.

-- Ken