This paper describes a newly designed multigigabit router (MGR) which 
achieves up to 32MPPS forwarding rates with 50 Gb/s of full-duplex 
backplane capacity.

The basic idea of the design is to separate the line cards and forwarding
engine cards into distinct parts connected by a high-speed backbone switch. 
Each line card can remove and send the header of incoming packet to the 
forward engine for processing and integrate the new header with the packet, 
and the forwarding engine reads the packet header to make routing decision 
and updates header information. A separate network processor is present to 
provide basic management functions.

There are five major innovations in this design: 
 1) the forwarding engine has a complete set of the routing tables; 
 2) a switched bus is used to achieve the high speed for its parallelism; 
 3) the design separates forwarding engines on board from the
line cards to enhance expediency and flexibility; 
 4) an abstract link layer header format is used; 
 5) MGR includes QoS processing supported by the forwarding engines.

The forwarding engine is built on Alpha 21164, a 64 bits 32 register 
superscalar RISC processor, and is responsible for routing decisions. This 
paper summarizes the key features for Alpha 21164 and describes how the 
forwarding engine hardware and software operations are related to those 
features. One important issue here is how to build up the routing table. 
The engine achieves it in two ways: 1. It uses ARP protocol at low 
frequency to collect link-layer addresses; 2. If it receives a datagram 
whose destination link-layer address is unknown, the engine will pass it to 
network processor which will do ARP. Network processor gets the information 
and passes it back to forwarding engine, which will insert the information 
into forwarding table then. One important point is that the router does not 
suffer from head of line blocking since each input keeps a separate FIFO 
and bids separately for each output. Details about implementation of the 
abstraction of link layer header are also discussed.

A 15-port point-to-point switch is used to move data between function 
cards. The allocation algorithm for the switch seeks to maximize throughput 
at the expense of predictable latency. Details of the switch and the 
allocator algorithm are introduced in the paper.

Then the paper moves on to the line card design. The inbound and outbound 
packet processes are completely disjoint. The inbound packet processing is 
rather simple, and the outbound packet processing is much more complex .

In the end, the paper provides brief discussions on network processor, 
which is a commercial PC motherboard with a PCI interface, and the 
management of routing and forwarding tables to demonstrate its advantages 
over traditional approaches.

However, the design is not flawless. First, separation of forward engine 
and line card introduces more traffic on the backplane switch, since the 
package header has to be sent through the switch to and from the forwarding 
engine for processing. Second, the switch needs very complicated algorithm 
to ensure the maximum usage of the switching capability. The detailed 
discussion of this algorithms complex is somewhat skipped. Third, the 
supporting of multicast is not so efficient since that the same message has 
to be duplicated before it is forwarded to more than one outbound line 
cards.

Overall, the important contributions of this MGR are: it shows that 
examining every datagram header at high speed is feasible and that router 
technology can continue to serve as a key component in high-speed networks.