Lecture Topics

• Last time: pipelining
• This time: gigabit Ethernet example
• Next time: <holiday – no class>
• Time after that: IP, TCP implementation

Pipelining review

• Validity rules
• To maximize performance: balance stages
• Latency always suffers
• Potentially a lot
• Queues add virtual pipeline stages
• Trix
• Duplicate long stages and run them in parallel
• “one outstanding request” (2-phase trick)
  req(0);
  while (1)
  {
    req(i+1);
    sync(i);
    i++;
  }

Forwarding definitions

• "routing" = = Layer 3 forwarding = = IP forwarding
• Based on destination IP address
  
• "switching" = = Layer 2 forwarding
• Based on destination MAC address

Intel Gigabit Ethernet example

• General structure
• (2) Gigabit Ethernet ports
• Processing tasks for each incoming packet
1. Determine which port to transmit packet out on
2. Determine the next hop MAC address
3. Modify Ethernet frame header
4. Modify IP packet header (TTL, checksum)


• Pipeline diagram
  



• Trix
• Multithreading
• Allows some parallel operations, but Reads/Writes to SDRAM must be initiated in order, so inter-thread signals are used for synchronization
• RFIFO/TFIFO units have FSM to operate in parallel with other units
• SDRAM can also operate in parallel with other units
• RDY bus has FSM to query MACs without microengines help

Pipeline Hardware

• To convert a single threaded processor pipeline to a multithreaded pipeline
• Need to maintain a separate PC for each thread
• Need bigger register file
• Usually divided into separate sections for each thread
• Prevents having to save registers to stack on context switch