CS2200 Spring 2005 Practice Exam The exam will essentially focus on material since about the second test. This practice test will give you a good idea of what to focus on and give you a rough idea of the types of questions you might be asked. Bring a powerful scientific caclulator with you to the exam. Virtual Memory 1. A processor has a 32 bit virtual memory address and a 32 bit physical memory address. Word size is 32 bits with 8 bit bytes and byte addressing is used. The page size is 256 bytes. How many entries are there in each processes page table? How many entries are there in the frame (reverse lookup) table? Regarding the virtual addresses how many bits comprise the virtual page number and how many bits comprise the offset? Regarding the physical addresses how many bits comprise the physical frame number and how many bits comprise the offset? Assuming each page table entry is 1 word long how big is the page table for each process? TLB 2. A processor has 32 bit virtual and physical addresses and uses byte addressing. Page size is 64 KB. The TLB (Translation Lookaside Buffer) only has 2 entries. (Okay, so this is a practice problem computer.) The current contents of the TLB are shown below. Values are in hexidecimal. TLB VPN V PFN FFFE 1 32 63BA 0 44 Describe in detail what happens when the following physical addresses are referenced by the processor. You should explain what the TLB does and what the memory does. For this problem ignore any other caches. FFFE1234 7F3B9012 63BA4044 Caching 3. A certain processor has a 32-bit physical addresses. Word size is 32 bits and each word consists of 4 8-bit bytes. Byte addressing is used. The processor is equipped with a 4-way set associative cache with 4 word (i.e. 16 byte) blocks. There are 32 KB available for cache data storage. Assume the cache is write-back and uses LRU replacement. Draw and label the cache. Show how a memory reference would be partitioned into tag, index and offset fields. How many total bits would be required to implement this cache? Make up address and cache contents to demonstrate a hit, a write miss and a read miss. For each describe in detail the sequence of operations to complete processing. Amdahl's Law 4. There is an old saying that a crash program is like getting 9 women pregnant in order to have a baby in 1 month. But seriously, using Amdahl's law explain why this doesn't work. Multi-threaded programming 5. Explain in some detail (using code to illustrate) exactly how mutex lock, unlock, wait and signal finctions work in the pthreads library. 6. Take your code from HW4 and draw out a diagram showing a typical sequence of operations. At various points in time indicate which threads are waiting for a mutex and which threads are waiting for a condition variable. Try to illustrate as many different cases as possible. Networking 7. Describe what each of the following hardware items does and is used for. Make sure to be specific by using the TCP/IP protocol stack in your description. NIC Hub Repeater Bridge Switch Router Project 8. Describe concisely exactly what you did in P5 and how it interacted with what we supplied you. I/O 9. Look on the web for information relating to Unix Inodes. Draw a diagram showing what an Inode looks like when it is the inode for the maximum possible file allowed in Unix. 10. Suppose a disk drive has 512 cylinders, numbered from 0 to 511. There are 6 platters and both sides of each are used. Each track has 32 sectors. Each sector holds 128 bytes. How many bytes per cylinder? How many bytes total on the drive? How many bytes per track? How many sectors per cylinder? Networking 11. Compare and contrast Ethernet with Token Ring 12. Explain what is meant by a collision domain. Include in your answer the interaction of hubs, repeater, bridges, switches and routers with collision domains. 13. Explain briefly the key ideas behind internetworking.