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CS3220 - Processor Design
Spring 2005
Tue/Thu 4:25-5:55, CCB 102
Prof. Gabriel Loh
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General Description: This post-2200 elective provides the
student with an in-depth study of concepts and principles for
designing pipelined processors. In particular, the course will
take a basics-first bottom-up approach, starting from the transistor
level and making our way up to a highly-detailed fully-pipelined processor.
Course Prereqs: CS2200
Anti-Prereqs: The begining of this course will cover some
material that feels ECE-ish, but it will be presented assuming
no previous background in electrical or computer engineering.
Project Component: Different from previous versions of this
course, the project component will be simulator based (in the past,
the project involved implementing processors on FPGA-based systems).
We will use a non-trivial instruction set architecture, implement an
assembler for the architecture, and then implement a detailed
behavioral and timing simulator of a pipelined processor that executes
programs generated by your assembler.
Versus Projects from CS3220 of the Past: The reason for switching to
a simulation-based approach is that the design phase of modern
processors is based primarily on simulation, and the implementation in
hardware description languages (which was used for the FPGA-based projects)
typically comes after the design portion of a project has been completed.
This is not to say that hardware description languages don't matter
anymore. On the contrary, I strongly recommend that any students that are
serious about pursuing a career in the microprocessor industry take such
courses in the ECE department.
Homework, Exams, Projects and Grading
Three problem sets (15% of grade)
Three Projects (50% of grade)
One mid-term exam (10% of grade)
One quiz Fourth Homework (5% of grade)
Final Exam (20% of grade)
Drop Date: Grades for all three homeworks and the mid-term will
be available prior to the drop date.
Office Hours
Immediately after class in my office (CCB221), from 6:00-7:00. If class
ends early, then there will be longer office hours (until 7:00).
Collaboration Policy
Collaboration, Cheating, Plagarism, etc.
Lecture Slides, Notes, etc.
Lecture 0 (ppt slides)
Notes on the XOR gate example (pdf)
Quine-McCluskey example (pdf)
Adder Notes (pdf)
Carry Save Adder Notes (pdf)
Multiply/Divide Notes (pdf)
"Mathematics of the Pentium Division Bug" (pdf), by Alan Edelman (appears in SIAM Review 39, 1997, pp. 54-67)
ISA Notes (pdf)
Cache Notes (pdf)
w75 Pipelining Notes (pdf)
Vector-Processing/SIMD Notes (pdf)
Deeper Pipelining Notes (pdf)
Superscalar Execution Notes (pdf)
Out-of-Order Execution Notes (pdf), by Jim Smith and Guri Sohi (UWisc)
Homework/Problem Sets
Homework 1 (pdf) Due Jan 27, 2005 in class. (Solutions)
Homework 2 (pdf) Due Feb 08, 2005 in class. (Solutions)
Homework 3 (pdf) Due Feb 22, 2005 in class. (Solutions)
Homework 4 (pdf) Due Mar 17, 2005 in class. (Solutions)
Midterm Solutions (pdf)
Homework/Problem Sets
Project 1 (pdf), Auxilliary test file (binary)
Project 2 (pdf) Due Mar 19, 2005 via email.
Project 3 (pdf) Due Apr 21, 2005 via email.
Auxilliary Files:
Tentative Schedule:
| Date | Week/Day | Topics | Other Notes |
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| Jan 11 | 1/Tue | Intro, Semiconductors, Transistors, CMOS | |
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| Jan 13 | 1/Thu | Logic gates, boolean functions, truth tables, K-maps, Quine-McCluskey | |
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| Jan 18 | 2/Tue | Numbers, Negatives, Simple Adders | |
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| Jan 20 | 2/Thu | More adders, parallel prefix, subtraction, shifters | HW1 handed out |
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| Jan 25 | 3/Tue | Multiplication (Wallace trees, Booth) | |
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| Jan 27 | 3/Thu | Division (iterative, SRT) | HW1 due |
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| Feb 1 | 4/Tue | Floating Point | HW2 handed out |
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| Feb 3 | 4/Thu | Clocks, Latches, Flip-flops, FSMs | |
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| Feb 8 | 5/Tue | Basic ISA concepts | HW2 due |
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| Feb 10 | 5/Thu | More ISA stuff, RISC vs. CISC, design tradeoffs | HW3 handed out |
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| Feb 15 | 6/Tue | The w75 ISA for our projects | Project 1 Handed Out |
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| Feb 17 | 6/Thu | Technology Symposium | |
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| Feb 22 | 7/Tue | Datapath and Control: 1-cycle CPU | |
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| Feb 24 | 7/Thu | Midterm Exam | |
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| Mar 1 | 8/Tue | Pipelining, hazards, interlocks, bypasses | |
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| Mar 3 | 8/Thu | Scoreboarding control logic | PRJ1 due, PRJ2 handed out, midterm grades returned (Mar 4 last day to drop) |
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| Mar 8 | 9/Tue | Caches, logic design of SRAMs | |
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| Mar 10 | 9/Thu | Memory hierarchy, locality, line size tradeoffs | |
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| Mar 15 | 10/Tue | HW Support for Virtual Memory | |
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| Mar 17 | 10/Thu | Branch Prediction | PRJ2 due, PRJ3 handed out |
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| Mar 22 | | Spring Break |
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| Mar 24 | |
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| Mar 29 | 11/Tue | Superscalar Pipelines | |
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| Mar 31 | 11/Thu | Vector Processing/SIMD | |
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| Apr 5 | 12/Tue | Deepening the pipe: fetch/decode | |
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| Apr 7 | 12/Thu | Deepening the pipe: register read, execute, bypass | |
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| Apr 12 | 13/Tue | Power: spikes, di/dt drops, clock gating, drowsy/sleep transistors | |
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| Apr 14 | 13/Thu | Battery life, hot spots: efficiency of pipelining, power-performance metrics, V/F scaling | |
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| Apr 19 | 14/Tue | Out of order processors | |
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| Apr 21 | 14/Thu | Multi-threading | PRJ3 due |
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| Apr 26 | 15/Tue | In the year 2000 (preview of future topics in CS4290, CS4803) | |
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| Apr 28 | 15/Thu | Open questions, review | PRJ3 due |
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| May 6 | Final: Friday, 8:00-10:50am, CoC 102 |
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