Deconstructing the LC2200-8

1. Major Subsystems

The Bus 

Recall from earlier that busses are nothing more than bundles of wires. The LC2200-8 uses busses to simplify the circuit connections between subsystems, but this is purely to reduce clutter. When a component puts a value "on the bus" all it has done is output to 8 wires which happened to be wrapped in a common schematic symbol and samed sequentially as bus0..bus7. The same applies for "reading the bus." Busses also must obey the same rules regarding contention as normal wires. You must use tristate logic to ensure that two values are driven onto the bus during the same clock cycle.

The Register File 

The LC2200-8 specification requires it to have a certain number of general purpose and special registers. The general purpose registers are contained in a schematic sub-circuit called the register file. Each register is linked to control logic and output logic which allows selection signals to control which register is currently active for reading or writing. You can open up the register file to see how it works and what will require changing as part of the project assignment. The inputs and outputs of the subcircuit are denoted with "ports" in LogicWorks. The outputs of the register file are wired to the bus using tristate logic.

The Arithmetic Logic Unit (ALU) 

The ALU is the part of the LC2200-8 which actually performs computation. It is contained in a subcircuit and has several arithmetic operations which may be selected by the values on the ALUfunc lines ALUHi and ALULo. For example, to get the ALU to add the values would be 0 and 0, respectively. The ALU subcircuit has its inputs wired to two special purpose registers, A and B, which serve as a holding place for argument values of an operation while the operation is in progress. Since only one value can be on the bus during any given clock cycle, the first argument must be stored in a register while the second argument is loaded before the actual computation may occur. Again, the outputs are wired to the bus using tristate logic.

Control Logic 

If the ALU were considered the muscle of the LC2200-8 then the control logic would function as the brain. The control logic is generated using a finite state machine and is wired to all the components of the system in order to control what happens when, where inputs come from, where outputs are written, and what instruction should come next. Specifically, you are asked to implement this FSM as a control ROM and a state register using a special tool written for the endeavor which translates a symbolic description of the FSM's states into binary data which can be loaded into the ROM in LogicWorks. For more information on this process, please see the comprehensive documentation on the FSM ROM generator provided with the project. One final element of the control logic which you are asked to implement is zero-detection on the bus. This can be a somewhat tricky issue since the state must be changed only when the control logic requests a zero-check and not every cycle. The LdZ signal is provided for this purpose, and a method of holding the value of the detection will need to be implemented using either a latch/flip-flop or a special purpose register. The detection of 0 on the bus should be done through conventional combinational logic on the 8 bus lines.

The Clock 

Initially your datapath does not have a clock device, the clock value must be manually toggled using a binary switch 9see below). At some point in your development, however, you will need to add a clock device which will automatically oscillate between high and low at a specified frequency in order to provide the clocking your datapath requires for operation. The datapath will be edge-triggered meaning that action occurs only on the edge of the clock cycle as it changes from 0 to 1. This clocking mechanism is the fundamental thing which makes the operation of the computer possible since it allows control over when things happen and thus enables sequential logic.

2. Built-in Debugging Mechanisms

Hex Keypads and Binary Switches 

Initially the datapath is wired up without a clock, and without a control FSM. In this configuration it must be run manually, changing the values on the bus using hex keypads and the values of control logic and the clock using binary switches. This is certainly tedious, but if you simulate the various LC2200-8 instructions manually in this way you will make certain that you understand how they should work and which control inputs will be required in your FSM control logic. As a record of the steps required to produce the desired output for an instruction you are simulating, you may refer to the clock diagram which will record the values of all the labeled wires vs. time.

Hex Displays and Binary Probes 

Once you have moved passed the initial examination of the datapath and begun to implement and connect control logic you will want to monitor what is going on in your circuit to determine if it is behaving in the way you expect. The easiest way to do this is to slow down the simulation and hook up hex displays and binary probes to the bus and control logic so that you can see the values changing in real time and determine when something unexpected is occurring. Again you may also want to look at the timing diagram for an overall look at what is happening in the datapath over time.

3. Understanding Finite State Machines in Control Logic

The FSM as a ROM 

One way to implement an FSM, and the way you will implement your FSM for the LC2200-8, is to put the control signals and state transitions into a ROM which can then be hooked up to a register which maintains state for the FSM. The inputs to the control logic, namely the opcode, control code, previous state, and Z values, are used as an address into the ROM. The contents at this address are passed out of the ROM and the outputs are connected to the various control signals which go to the datapath as well as to the state register which latches the value to be used in the next clock cycle as the new current state. The ROM must, therefore, be large enough to index data at addresses corresponding to all possible combinations of the input and each entry must be large enough to hold all possible combinations of output control signals. The process of translating your symbolic FSM description into actual binary data to be inserted into the FSM ROM is abstracted much in the same way that a compiler abstracts the transition from source to binary.

The State Register 

The state register functions as a buffer between the current and next cycles of the computer. The current cycle state output value is latched into the register so that it can be supplied as an input to the current state in the next cycle. This process allows the FSM to maintain state and allows transitions from one state to another each clock cycle.