Lecture Notes/Slides Lecture Notes Supplementary materials protected by their own individual copyrights. Please do not copy, redistribute, etc. Lecture 1: Intro and Performance Lecture 2: Other Metrics Smoking CPU Video Lecture 3: Pipelining Review (S&L, 2) Lecture 4: Superscalar Review (S&L, 4) Original Tomasulo's Algorithm Paper, 1967 (pdf) Lynn Conway's Dynamic Instruction Scheduling Paper, 1966 (html) Lecture 5: Instruction Fetch (S&L, 4.3.1, 5.1) Lecture 6: Branch Prediction (S&L, 9.2-9.4) Lecture 7: Advanced Fetch (S&L, 9.5) Original Collapsing Buffer Paper (pdf) Lecture 8: Advanced Fetch (S&L, 4.3.2) Lecture 9: Register Renaming (S&L, 5.2) Lecture 10: Instruction Scheduling (1) (S&L, 5.2) Lecture 11: Instruction Scheduling (2) Lecture 12: ALUs and Bypass (S&L 2.2.3.3-2.2.3.5) Lecture 13: Memory Scheduling (S&L 5.3,10.1,10.2,10.4) Lecture 14: Caches and Memory (S&L 3.3-3.4.3,3.6) Lecture 15: Commit Lecture 16: DRAM and Prefetching Lecture 17: Multi-This, Multi-That, ... (S&L 11) Reading for Case Studies Pentium-Pro Shen and Lipasti: Chapter 7 "Intel's P6 Microarchitecture", Colwell et al. Tuning the Pentium Pro Microarchitecture, Papworth (Don't bother trying to read the grey section on the third page (pg. 10) since the poor scanning makes it pretty much illegible.) Alpha 21264 The Alpha 21264 Microprocessor, Kessler Circuit Implementation of a 600MHz Superscalar RISC Microprocessor, Matson et al. We briefly mentioned CAM-based renamers. See Section 2.1 of the paper Physical Register Inlining (Lipasti et al.) for a good explanation of how this works. Pentium 4 The Microarchitecture of the Pentium 4 Processor, Hinton et al. A 0.18um CMOS IA-32 Processor with a 4-GHz Integer Execution Unit, Hinton et al. The Intel Pentium 4 Processor, Carmean (talk slides); if you're interested in seeing the original talk, follow this link AMD K7/K8 The AMD Athlon XP Processor with 512KB L2 Cache, Huynh (white paper) The AMD Opteron Processor for Multiprocessor Servers, Keltcher et al. AMD's Next Generation Microprocesor Architecture, Weber (MPF talk slides) AMD's Hammer micro architecture preview, de Vries (Opteron reverse engineering based on analysis of patents) Pentium-M The Intel Pentium M Processor: Microarchitecture and Performance, Gochman et al. Let's speculate and try to decipher the details of the next-generation Pentium-M: Fall IDF 2005 - Day 1: Intel's New Architecture Details Revealed, Lai Shimpi Fall IDF 2005: Intel's unified processor architecture, Hannibal Intel reveals details of new CPU design, Wasson Itanium 2 and Montecito Itanium 2 Processor Microarchitecture, McNairy et al. Montecito: A Dual-Core, Dual-Thread Itanium Processor, McNairy et al. Power4, Power5 Power4 System Design for High Reliability, Bossen et al. IBM Power5 Chip: A Dual-Core Multithreaded Processor, Kalla et al. UltraSPARC, Niagara UltraSPARC-III: Designing Third-Generation 64-Bit Performance, Horel et al. Niagara: A 32-Way Multithreaded SPARC Processor, Kongetira et al. IBM/Sony Cell Power Efficient Processor Architecture and The Cell Processor, Hogstee Power-Conscious Design of the Cell Processor's Synergistic Processor Element, Takahashi et al. Web Links WWW Computer Architecture Page: Listing of conferences, people, other comp arch information. USENET comp.arch: Internet newsgroup, unfortunately the signal-to-noise ratio has dropped over recent years. Real World Technologies: A more technical forum with IMO higher quality discussions than comp.arch, but the posting activity is lower. Also has some interesting articles. Tom's Hardware: More consumer and enthusiast oriented, but has some interesting high-level descriptions of processor architectures and all of the latest benchmark results. At Random: Monthly column in the IEEE Computer Society magazine from Bob Colwell (chief architect of multiple Pentiums). Not all articles are about processors, but they're almost always entertaining to read. Intel Microprocessor Hall of Fame: Stroll down memory-lane starting from the original 4004. Die photos for most older CPUs. Only goes up to the first P4.