Notes/Slides

• L1 - Intro (pdf)
• L2 - Verilog (pdf)
• L3 - Testbenches and Basic FSMs (pdf)
• L4 - FPGAs and Example (pdf); DCM detail (pdf)
• L5 - More on FSMs (pdf)
• L6 - Project ISA (pdf)
  • Project ISA Document (pdf)
• LX - Pipelining Review: See Patterson and Hennessy "Computer Organization and Design: the Hardware-Software Interface" (4th ed.)
• L7 - Behavioral Verilog (pdf)
• L8 - Memory (pdf)
• L9 - Logic Optimization (pdf)
• More detailed explanation/example of Quine-McCluskey (pdf)
• Notes on Faster Adders (pdf)
• Notes on Multiplication and Division (pdf)
• L10 - Timing (pdf)
• L11 - Verification (pdf)

Links

• Karnaugh Map Tutorial
• Xilinx ISE 10.1 Tutorial
• Very Brief Verilog Overview
• Spartan-3E FPGA chip Manual (just the chip)
• Spartan-3E Starter Kit Manual (the chip+board)

Other Stuff

• module1.v (8/28/08)
• wide_add.v (8/28/08)
• AOI.v (9/02/08)
• AOI_test_pre.v (9/02/08)
• counter.v (9/02/08)
• counter_tb.v (9/02/08)
• The follow are the files from the example used in class on 9/04/08. Try creating a new project and adding the LED_test.v and LED_test_tb.v files. Compile and run the test-bench through the behavioral simulator to verify that it all works. Then create a new file for your top-level module (I called it base, you can call it whatever). Define the ports that connect to the outside world (the pins), instantiate the module, instantiate the DCM, and then connect everything up. You should end up with something like base_complete.v (I've included those files below for your reference in case you get stuck). Then do the pin assignments with the PACE tool, synthesize, place and route, and generate the programming file. When your group has received its FPGA board, try downloading the bitstream to the board to make sure everything works.
  Note: When starting a new project, use the following settings. Family: Spartan 3E, Device: XC3S500E, Package: FG320, Speed: -4. All other defaults should be fine.
  • LED_test.v - This is the module.
  • LED_test_tb.v - Stand-alone test-bench for the above module.
  • base.v - This is the top-level module, but without the DCM instantiated and relevant connections.
  • base_complete.v - The top-level module, but with the DCM and related connections.