; ; 8-Apr-98 ; ; RCS: $Id$ ; Lecture notes for Wednesday, 8-Apr-98 This lecture was the second of two reviewing digital logic basics. These lectures follow the flow of topics in Appendix B of the text pretty closely. There were two main topics here: circuits with state, and then FSMs in detail. 1. Circuits with state. A circuit that can hold a stable value indefinitely is said to have "state". You can construct such circuits by adding feedback paths around a combinational logic circuit, i.e. by constructing logical circuits with cycles. However, adding cycles can also be used to make circuits oscillate, to give indefinite output values (neither one nor zero) and just generally trash the digital abstraction. Arbitrary circuits with state are difficult to reason about, so in practice we contrain the design space heavily by (a) encapsulating state in only a very small set of primitives and (b) defining a clocking strategy. The result is a set of designs that are much easier to reason about. The sections below talk about primitives, clocking, diverge momentarily into memories, then give an example of finite-state machines. 2. Primitives. [we did some of this last time] RS-latches illustrate the basic effect of using feedback for state and gates for control. Cross-coupled NAND gates have a truth table like this: R_ S_ | Q Q_ --------------- 1 1 | Q Q_ i.e. hold state indefinitely 0 1 | 0 1 cause Q to be reset 1 0 | 1 0 cause Q to be set 0 0 | 1 1 unused combination An RS-latch is simple but not terribly usable. A little bit of circuitry around an RS-latch gives you a D-latch: E | Q ----- 0 | Q hold state indefinitely 1 | D copy D to Q (transparent) D-latches still have the problem that they are sometimes transparent. You can't wrap combinational feedback around a D-latch and make a state machine (our ultimate objective) because of this transparency. The D-flip-flop (internally two back-to-back D latches) solves the problem by copying D to Q only on the positive edge of its "clock" input (conventionally marked ">"). You can't really draw a truth table for a D-flip-flop, but here's an improvisation: > | Q -------- 0 | Q hold state indefinitely 1 | Q hold state indefinitely 1->0 | Q hold state indefinitely 0->1 | D copy on transition. D-latches and D-flip-flops may be combined into wider, multibit components. 3. Clock discipline. Even the well-defined primitives can be composed in extremely hard-to-analyze ways, so a further simplification in standard practice is to legislate simple timing throughout a design via a global "clock discipline" for a circuit. The simplest clock discipline is the single edge-triggered clock, which we will use exclusively. In the edge-triggered clock discipline, the circuit obeys the following rules: a. There are no combinational cycles; any "cycle" in the circuit includes an edge-triggered flip-flop. b. All of the flip-flops use the same, global clock which is driven by a regular square wave. c. The period of the clock is "long enough" to accomodate any delay in the circuit. More on that later. 4. Memories. A familiar circuit with state is RAM -- random access memory -- the hardware equivalent of an array in a programming language. Memories are usually built out of latches. A multiplexor is used to select the latch to read and a decoder is used to select the latch to write. A memory may have multiple read and write "ports" by using multiple read multiplexors and write decoders. Large, dense memories play more elaborate tricks to reduce the size of the memory cells. Large SRAMs use a 2D array of minimal latches. A decoder selects which row is to be addressed. Reading is accomplished by reading the whole row and then using a multiplexor to select the bit from the row. Writing is accomplished using an electrical trick to "overdrive" the latch backwards through the multiplexor to change the state of the latch. The densest possible memories are even more exotic. DRAMs use capacitors to store bits and need no latches at all. Each DRAM cell needs one capacitor for storage and one transistor for the select logic (SRAMs, which use the most minimal form of latches, end up with 4 or 6 transistors per cell). The "dynamic" in DRAM comes from the fact that the charge on the capacitors slowly dissapates (on a scale of milliseconds) so the memories need to be "refreshed" (read and then re-written) constantly. 5. Finite State Machines (FSMs). FSMs may be familiar as the "finite automata" formalism from theory of computation. An FSM is a block of logic with a finite number of inputs, a finite number of outputs and a finite set of internal "states". I.e. somewhere inside the box is some memory that remembers the state: --------- n | | m n inputs ---/-->| FSM |----/--> m outputs --->|> | | --------- clock ----- The outputs of the FSM are a function of the current state (and sometimes of the input, too). The state changes only at identifyable points (i.e. at the positive edges of the clock input signal) and the next state is a function of the current state and inputs. next state = f(state, inputs) outputs = f(state, [inputs]) In the style of FSM we will use, the outputs are always a function of the state alone (a "Moore machine"). The other style (a "Mealy machine") is possible but has some timing-related drawbacks. The operation of an FSM is conveniently described using a state-transition diagram (see homework 1 for an illustration). The state-transition diagram consists of balloons and arrows. Each balloon represents a state. Balloons are labelled with the name of the state and (in a Moore machine at least) may also be labelled with the values of the outputs for that state. Each arrow represents a transition between states. The arrows are labelled with the input condition (a boolean function of the inputs) that is required for that transition to be taken. The labels on the arrows are often reduced to a minimal form representing *only* the inputs on which the transition depends, which can be confusing. As an extreme, if the transition depends on nothing (it always occurs), then the arrow may be labelled with "1" (always true) or with no label. Any (Moore type) finite-state machine may be synthesized using the following standard circuit: k /------------------/------\ | --------- | --------- | | | | | | \----| next | ---- | | output| m n | state |-----|DQ|------| ROM |---/---- outputs inputs ----/---| ROM | |> | | | | | ---- | | --------- --------- I.e. two ROMs (representing combinational logic) and a register. The register must have at least enough bits (k bits) to represent all the states in the state diagram. The number of inputs and outputs (n and m in this diagram) are generally given as part of the problem. The next state ROM implements the next state as a function of the inputs and the current state, f(inputs, state), while the output ROM implements the output as a function of the current state, f(state). The encoding of the two ROMs may be derived directly from the state transition diagram. First, assign k-bit binary numbers to each of the states. Next, draw a truth table for the next-state ROM (k + n inputs, k outputs). The entries for that truth table may be found by inspecting the state-transition diagram, i.e. for each state & combination of inputs, write what the next state will be. Finally, draw a truth table for the output ROM and fill it in, i.e. for each state, what will the output be. It's appropriate to use Xs in the inputs and outputs of the truth tables for input and output combinations that don't matter. Xs in an input allow one line to represent multiple lines in the truth table. Xs in outputs would be useful if we were to go and derive minimal circuits (e.g. with Karnaugh maps) for random gates or a PLA. With a ROM, though, all unused outputs might as well be zero. 6. Timing and the dynamic discipline. The static discipline gave us the rules for combinational logic: thou shalt give the circuit valid 1s and 0s, wait at least a propagation delay time and the circuit will respond with valid 1s and 0s on the output. The dynamic discipline is the counterpart for circuits with state. The essential rule is "the data inputs to a state-storing primitive shall remain valid, stable & constant during the sampling interval". The rule is specified for a particular primitive in terms of timing requirements for the inputs to the primitive. For instance, for a D-flip-flop, there is a requirement that the D input be stable at least a setup time (T_setup) before the rising clock edge and remain valid at least a hold time (T_hold) after the falling clock edge. The two timing values define an interval in which the D input must be valid and stable. For instance, the implication of the dynamic discipline in our FSM design employing the edge-triggered clocking discipline is that the period of the global clock must be long enough to accomodate the time for a signal to propagate from the state register, through the next-state register, and still meet the setup time of the state register. The consequences of violating the dynamic discipline are similar that of the static discipline: all bets are off and truly bizarre things can happen. For instance, the output can become invalid and sometimes remain invalid for even longer than the propagation delay of the register (!!).