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;							28-Apr-98
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; RCS: $Id$
; Lecture notes for Monday, 27-Apr-98

This lecture hit two points: interfacing multiple memory modules to a
single-bus processor (or any processor) and the construction of
ALUs/adders.

My discussion of arithmetic circuits is following chapter 4 pretty
closely, so I'll skip writing about that.

1. Memory interfacing.

   The single-bus circuit lumps all the elements of the computer
   together.  In practice, the processor is usually on one chip and
   the memory is external on other chips.  We can divide up the
   diagram like this:

		processor			64K-word
		(w/out memory)			memory module

		---------			---------
	    	|	|   32		    16	|	|
		|   addr|---/-->	----/-->|addr	|
	    	|	|   32		    32	|	|
		|   data|<--/-->	<---/-->|data	|
	    	|	|   		    	|	|
		|  write|------>	------->|write	|
	  	|	|		------->|enable	|
		---------			---------

      Processor: The address		Memory: a 64K-word RAM takes
      is the output of the MAR,		only 16 bits of address.
      the data bus is an extension	The "enable" signal must be
      of the internal bus and		"1" for the module to read or
      "write" is WrRAM			write.

   If the two boxes represent individual chips, the wires between them
   are wires on the circuit board that connects the chips.

   The bidirectional data bus deserves a little more detail.  That bus
   is connected to the internals of the processor and memory modules
   using back-to-back tri-state buffers as needed, like this:

		(processor)   |		 |   (memory module)
		 (one chip)		      (a few chips)
			      |		 |
       WrRAM --------\        
	(= write)    |        |		 |     
	            |\      	external	       
   processor    /---| >-----\ |	data bus | /----------> Din to RAM
    internal ---|   |/      |--------------|   
      bus       |     /|    | |	  	 | |     /|    
	        \----< |----/		   \----< |<--- Dout from RAM
	              \|      |		 |       \|    
	              |     		         |     
       DrRAM ---------/	      |		 |       \----- enable & not(write)

   The circuit must be arranged so that external data bus is driven by
   only one tri-state buffer at a time.

   The pair of back-to-back tri-states partitioning the processor's
   internal bus from the external data bus is not really required for
   logical reasons, but is a standard practice for electrical reasons.
   On-chip wires (e.g. internal to a processor chip) have different
   characteristics from off-chip wires, so you use buffers at the edge
   of the chip.

2. The RAM has only 64K words instead of 4G words, so it takes only 16
   bits of address.  If you only have *one* of these 64K-word RAM
   modules, the simplest thing to do is to wire the 16 bits of the RAM
   address to the lower 16 bits of the address coming from the
   processor and ignore the upper 16 bits:

		---------	    16		---------
	    	|PROC	|   32	  /-/--...   	|MEM	|
		|   addr|---/----<	    16 	|	|
	    	|	|     	  \---------/-->|addr	|
	    	|	|   32		    32	|	|
		|   data|<--/---------------/-->|data	|
	    	|	|   		    	|	|
		|  write|---------------------->|write	|
	  	|	|		1------>|enable	|
		---------			---------

   This wiring works fine (this is how the skeleton simulator for
   Project 2 is wired), except that it has the peculiar effect that
   the one RAM appears to "replicated" in the address space of the
   processor.  I.e., address 0x00010000 addresses the same location as
   address 0x00000000 since the top 16 bits of the address are
   ignored.  For practical purposes, this duplication doesn't matter
   since the program will not ordinarily look at addresses above
   0x0000ffff, but it can lead to weird bugs!

3. Suppose, though, you need more memory and want to wire more than
   one memory module to the same processor.

   The multiple modules may have addr/data/write wired in parallel,
   but the enable signals on the two modules must be wired so that
   only exactly one is enabled at any given momemt.

   The trick is to compute the enable for each RAM as a function of
   the high-order bits of the address.  For instance, with two
   64K-word RAMs, A and B, make enable_A = NOT(A16) and enable_B =
   A16.  That makes RAM A appear in the address range
   0x00000000-0x0000ffff and RAM B in address range
   0x00010000-0x0001ffff.

   Of course, since A17-A31 are still being ignored, RAM A appears
   again in the range 0x00020000-0x0002ffff, RAM B in
   0x00030000-0x0003ffff and so on.