memory[0]=33026
memory[1]=98304
memory[2]=12345
@@@
state before cycle 0 starts
	pc 0
	data memory:
		dataMem[ 0 ] 33026
		dataMem[ 1 ] 98304
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 0
	IDEX:
		instruction noop 0 0 0
		pcPlus1 0
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 1 starts
	pc 1
	data memory:
		dataMem[ 0 ] 33026
		dataMem[ 1 ] 98304
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction lw 0 1 2
		pcPlus1 1
	IDEX:
		instruction noop 0 0 0
		pcPlus1 0
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 2 starts
	pc 2
	data memory:
		dataMem[ 0 ] 33026
		dataMem[ 1 ] 98304
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction halt 0 0 0
		pcPlus1 2
	IDEX:
		instruction lw 0 1 2
		pcPlus1 1
		readRegA 0
		readRegB 0
		offset 2
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 3 starts
	pc 3
	data memory:
		dataMem[ 0 ] 33026
		dataMem[ 1 ] 98304
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 6 0 57
		pcPlus1 3
	IDEX:
		instruction halt 0 0 0
		pcPlus1 2
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction lw 0 1 2
		aluOutput 2
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 4 starts
	pc 4
	data memory:
		dataMem[ 0 ] 33026
		dataMem[ 1 ] 98304
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 0 0 0
		pcPlus1 4
	IDEX:
		instruction add 6 0 57
		pcPlus1 3
		readRegA 0
		readRegB 0
		offset 57
	EXMEM:
		instruction halt 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction lw 0 1 2
		loadMemData 12345
		aluOutput 2
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 5 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33026
		dataMem[ 1 ] 98304
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 12345
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 0 0 0
		pcPlus1 5
	IDEX:
		instruction add 0 0 0
		pcPlus1 4
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction add 6 0 57
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction halt 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction lw 0 1 2
		writeRegData 12345
machine halted
total of 5 cycles executed