memory[0]=33028
memory[1]=33285
memory[2]=2563
memory[3]=98304
memory[4]=12345
memory[5]=11111
@@@
state before cycle 0 starts
	pc 0
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 0
	IDEX:
		instruction noop 0 0 0
		pcPlus1 0
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 1 starts
	pc 1
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction lw 0 1 4
		pcPlus1 1
	IDEX:
		instruction noop 0 0 0
		pcPlus1 0
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 2 starts
	pc 2
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction lw 0 2 5
		pcPlus1 2
	IDEX:
		instruction lw 0 1 4
		pcPlus1 1
		readRegA 0
		readRegB 0
		offset 4
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 3 starts
	pc 3
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 2 3
		pcPlus1 3
	IDEX:
		instruction lw 0 2 5
		pcPlus1 2
		readRegA 0
		readRegB 0
		offset 5
	EXMEM:
		instruction lw 0 1 4
		aluOutput 4
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 4 starts
	pc 3
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 2 3
		pcPlus1 3
	IDEX:
		instruction noop 0 0 0
		pcPlus1 3
		readRegA 0
		readRegB 0
		offset 3
	EXMEM:
		instruction lw 0 2 5
		aluOutput 5
		readRegB 0
	MEMWB:
		instruction lw 0 1 4
		loadMemData 12345
		aluOutput 4
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 5 starts
	pc 4
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 12345
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction halt 0 0 0
		pcPlus1 4
	IDEX:
		instruction add 1 2 3
		pcPlus1 3
		readRegA 0
		readRegB 0
		offset 3
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction lw 0 2 5
		loadMemData 11111
		aluOutput 5
	WBEND:
		instruction lw 0 1 4
		writeRegData 12345
@@@
state before cycle 6 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 12345
		reg[ 2 ] 11111
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 6 0 57
		pcPlus1 5
	IDEX:
		instruction halt 0 0 0
		pcPlus1 4
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction add 1 2 3
		aluOutput 23456
		readRegB 11111
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction lw 0 2 5
		writeRegData 11111
@@@
state before cycle 7 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 12345
		reg[ 2 ] 11111
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 5 3 103
		pcPlus1 6
	IDEX:
		instruction add 6 0 57
		pcPlus1 5
		readRegA 0
		readRegB 0
		offset 57
	EXMEM:
		instruction halt 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction add 1 2 3
		loadMemData 0
		aluOutput 23456
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 8 starts
	pc 7
	data memory:
		dataMem[ 0 ] 33028
		dataMem[ 1 ] 33285
		dataMem[ 2 ] 2563
		dataMem[ 3 ] 98304
		dataMem[ 4 ] 12345
		dataMem[ 5 ] 11111
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 12345
		reg[ 2 ] 11111
		reg[ 3 ] 23456
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 0 0 0
		pcPlus1 7
	IDEX:
		instruction add 5 3 103
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset 103
	EXMEM:
		instruction add 6 0 57
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction halt 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction add 1 2 3
		writeRegData 23456
machine halted
total of 8 cycles executed