memory[0]=33032
memory[1]=33289
memory[2]=3076
memory[3]=2561
memory[4]=65793
memory[5]=65788
memory[6]=50186
memory[7]=98304
memory[8]=4
memory[9]=-1
memory[10]=0
@@@
state before cycle 0 starts
	pc 0
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 0
	IDEX:
		instruction noop 0 0 0
		pcPlus1 0
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 1 starts
	pc 1
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction lw 0 1 8
		pcPlus1 1
	IDEX:
		instruction noop 0 0 0
		pcPlus1 0
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 2 starts
	pc 2
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction lw 0 2 9
		pcPlus1 2
	IDEX:
		instruction lw 0 1 8
		pcPlus1 1
		readRegA 0
		readRegB 0
		offset 8
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 3 starts
	pc 3
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 4 4
		pcPlus1 3
	IDEX:
		instruction lw 0 2 9
		pcPlus1 2
		readRegA 0
		readRegB 0
		offset 9
	EXMEM:
		instruction lw 0 1 8
		aluOutput 8
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 4 starts
	pc 4
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 2 1
		pcPlus1 4
	IDEX:
		instruction add 1 4 4
		pcPlus1 3
		readRegA 0
		readRegB 0
		offset 4
	EXMEM:
		instruction lw 0 2 9
		aluOutput 9
		readRegB 0
	MEMWB:
		instruction lw 0 1 8
		loadMemData 4
		aluOutput 8
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 5 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 4
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction beq 0 1 1
		pcPlus1 5
	IDEX:
		instruction add 1 2 1
		pcPlus1 4
		readRegA 0
		readRegB 0
		offset 1
	EXMEM:
		instruction add 1 4 4
		aluOutput 4
		readRegB 0
	MEMWB:
		instruction lw 0 2 9
		loadMemData -1
		aluOutput 9
	WBEND:
		instruction lw 0 1 8
		writeRegData 4
@@@
state before cycle 6 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 4
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 6
	IDEX:
		instruction beq 0 1 1
		pcPlus1 5
		readRegA 0
		readRegB 4
		offset 1
	EXMEM:
		instruction add 1 2 1
		aluOutput 3
		readRegB -1
	MEMWB:
		instruction add 1 4 4
		loadMemData 0
		aluOutput 4
	WBEND:
		instruction lw 0 2 9
		writeRegData -1
@@@
state before cycle 7 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 4
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 4
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 7
	IDEX:
		instruction noop 0 0 0
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction beq 0 1 1
		aluOutput 0
		readRegB 3
	MEMWB:
		instruction add 1 2 1
		loadMemData 0
		aluOutput 3
	WBEND:
		instruction add 1 4 4
		writeRegData 4
@@@
state before cycle 8 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 3
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 4
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction beq 0 0 252
		pcPlus1 6
	IDEX:
		instruction noop 0 0 0
		pcPlus1 7
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction beq 0 1 1
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction add 1 2 1
		writeRegData 3
@@@
state before cycle 9 starts
	pc 2
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 3
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 4
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 7
	IDEX:
		instruction beq 0 0 252
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset -4
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction beq 0 1 1
		writeRegData 0
@@@
state before cycle 10 starts
	pc 3
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 3
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 4
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 4 4
		pcPlus1 3
	IDEX:
		instruction noop 0 0 0
		pcPlus1 7
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction beq 0 0 252
		aluOutput 1
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 11 starts
	pc 4
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 3
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 4
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 2 1
		pcPlus1 4
	IDEX:
		instruction add 1 4 4
		pcPlus1 3
		readRegA 3
		readRegB 4
		offset 4
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction beq 0 0 252
		loadMemData 0
		aluOutput 1
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 12 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 3
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 4
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction beq 0 1 1
		pcPlus1 5
	IDEX:
		instruction add 1 2 1
		pcPlus1 4
		readRegA 3
		readRegB -1
		offset 1
	EXMEM:
		instruction add 1 4 4
		aluOutput 7
		readRegB 4
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction beq 0 0 252
		writeRegData 0
@@@
state before cycle 13 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 3
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 4
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 6
	IDEX:
		instruction beq 0 1 1
		pcPlus1 5
		readRegA 0
		readRegB 3
		offset 1
	EXMEM:
		instruction add 1 2 1
		aluOutput 2
		readRegB -1
	MEMWB:
		instruction add 1 4 4
		loadMemData 0
		aluOutput 7
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 14 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 3
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 7
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 7
	IDEX:
		instruction noop 0 0 0
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction beq 0 1 1
		aluOutput 0
		readRegB 2
	MEMWB:
		instruction add 1 2 1
		loadMemData 0
		aluOutput 2
	WBEND:
		instruction add 1 4 4
		writeRegData 7
@@@
state before cycle 15 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 2
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 7
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction beq 0 0 252
		pcPlus1 6
	IDEX:
		instruction noop 0 0 0
		pcPlus1 7
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction beq 0 1 1
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction add 1 2 1
		writeRegData 2
@@@
state before cycle 16 starts
	pc 2
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 2
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 7
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 7
	IDEX:
		instruction beq 0 0 252
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset -4
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction beq 0 1 1
		writeRegData 0
@@@
state before cycle 17 starts
	pc 3
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 2
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 7
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 4 4
		pcPlus1 3
	IDEX:
		instruction noop 0 0 0
		pcPlus1 7
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction beq 0 0 252
		aluOutput 1
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 18 starts
	pc 4
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 2
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 7
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 2 1
		pcPlus1 4
	IDEX:
		instruction add 1 4 4
		pcPlus1 3
		readRegA 2
		readRegB 7
		offset 4
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction beq 0 0 252
		loadMemData 0
		aluOutput 1
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 19 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 2
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 7
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction beq 0 1 1
		pcPlus1 5
	IDEX:
		instruction add 1 2 1
		pcPlus1 4
		readRegA 2
		readRegB -1
		offset 1
	EXMEM:
		instruction add 1 4 4
		aluOutput 9
		readRegB 7
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction beq 0 0 252
		writeRegData 0
@@@
state before cycle 20 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 2
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 7
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 6
	IDEX:
		instruction beq 0 1 1
		pcPlus1 5
		readRegA 0
		readRegB 2
		offset 1
	EXMEM:
		instruction add 1 2 1
		aluOutput 1
		readRegB -1
	MEMWB:
		instruction add 1 4 4
		loadMemData 0
		aluOutput 9
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 21 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 2
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 9
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 7
	IDEX:
		instruction noop 0 0 0
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction beq 0 1 1
		aluOutput 0
		readRegB 1
	MEMWB:
		instruction add 1 2 1
		loadMemData 0
		aluOutput 1
	WBEND:
		instruction add 1 4 4
		writeRegData 9
@@@
state before cycle 22 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 1
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 9
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction beq 0 0 252
		pcPlus1 6
	IDEX:
		instruction noop 0 0 0
		pcPlus1 7
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction beq 0 1 1
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction add 1 2 1
		writeRegData 1
@@@
state before cycle 23 starts
	pc 2
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 1
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 9
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 7
	IDEX:
		instruction beq 0 0 252
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset -4
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction beq 0 1 1
		writeRegData 0
@@@
state before cycle 24 starts
	pc 3
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 1
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 9
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 4 4
		pcPlus1 3
	IDEX:
		instruction noop 0 0 0
		pcPlus1 7
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction beq 0 0 252
		aluOutput 1
		readRegB 0
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 25 starts
	pc 4
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 1
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 9
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 1 2 1
		pcPlus1 4
	IDEX:
		instruction add 1 4 4
		pcPlus1 3
		readRegA 1
		readRegB 9
		offset 4
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction beq 0 0 252
		loadMemData 0
		aluOutput 1
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 26 starts
	pc 5
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 1
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 9
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction beq 0 1 1
		pcPlus1 5
	IDEX:
		instruction add 1 2 1
		pcPlus1 4
		readRegA 1
		readRegB -1
		offset 1
	EXMEM:
		instruction add 1 4 4
		aluOutput 10
		readRegB 9
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction beq 0 0 252
		writeRegData 0
@@@
state before cycle 27 starts
	pc 6
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 1
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 9
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction noop 0 0 0
		pcPlus1 6
	IDEX:
		instruction beq 0 1 1
		pcPlus1 5
		readRegA 0
		readRegB 1
		offset 1
	EXMEM:
		instruction add 1 2 1
		aluOutput 0
		readRegB -1
	MEMWB:
		instruction add 1 4 4
		loadMemData 0
		aluOutput 10
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 28 starts
	pc 7
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 1
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 10
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction sw 0 4 10
		pcPlus1 7
	IDEX:
		instruction noop 0 0 0
		pcPlus1 6
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction beq 0 1 1
		aluOutput 1
		readRegB 0
	MEMWB:
		instruction add 1 2 1
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction add 1 4 4
		writeRegData 10
@@@
state before cycle 29 starts
	pc 8
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 10
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction halt 0 0 0
		pcPlus1 8
	IDEX:
		instruction sw 0 4 10
		pcPlus1 7
		readRegA 0
		readRegB 10
		offset 10
	EXMEM:
		instruction noop 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction beq 0 1 1
		loadMemData 0
		aluOutput 1
	WBEND:
		instruction add 1 2 1
		writeRegData 0
@@@
state before cycle 30 starts
	pc 9
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 10
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 0 0 4
		pcPlus1 9
	IDEX:
		instruction halt 0 0 0
		pcPlus1 8
		readRegA 0
		readRegB 0
		offset 0
	EXMEM:
		instruction sw 0 4 10
		aluOutput 10
		readRegB 10
	MEMWB:
		instruction noop 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction beq 0 1 1
		writeRegData 0
@@@
state before cycle 31 starts
	pc 10
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 10
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 10
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction data 7 7 255
		pcPlus1 10
	IDEX:
		instruction add 0 0 4
		pcPlus1 9
		readRegA 0
		readRegB 0
		offset 4
	EXMEM:
		instruction halt 0 0 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction sw 0 4 10
		loadMemData 0
		aluOutput 10
	WBEND:
		instruction noop 0 0 0
		writeRegData 0
@@@
state before cycle 32 starts
	pc 11
	data memory:
		dataMem[ 0 ] 33032
		dataMem[ 1 ] 33289
		dataMem[ 2 ] 3076
		dataMem[ 3 ] 2561
		dataMem[ 4 ] 65793
		dataMem[ 5 ] 65788
		dataMem[ 6 ] 50186
		dataMem[ 7 ] 98304
		dataMem[ 8 ] 4
		dataMem[ 9 ] -1
		dataMem[ 10 ] 10
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] -1
		reg[ 3 ] 0
		reg[ 4 ] 10
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction add 0 0 0
		pcPlus1 11
	IDEX:
		instruction data 7 7 255
		pcPlus1 10
		readRegA 0
		readRegB 0
		offset -1
	EXMEM:
		instruction add 0 0 4
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction halt 0 0 0
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction sw 0 4 10
		writeRegData 0
machine halted
total of 32 cycles executed