The DLX Architecture · Defining an instruction set: 1. Data types 2. Addressing Modes 3. Operations 4. Definition of register set · DLX: Generic Load/Store Architecture 1. Data types: Integer: 8-bit bytes, 16-bit half-words, 32-bit words Floating point: 32-bit single precision, 64-bit double precision Fixed-length instructions: 32 bits 2. Addressing Modes Memory is byte-addressible Big-endian (bytes number 0, 1, 2, ... in memory; left-most bit represents high-order bits) Big-endian machines: SPARC, 680x0 Little-endian: DEC, Intel 32-bit memory addresses All memory references through loads and stores between memory and either GPRs (general purpose registers) or FPRs (floating point registers) Can also move between GPRs and FPRs Only three data addressing modes: register, immediate and displacement: Mode Example Means Used for Register Add R4, R2, R3 R4 <- R2 + R3 Values in register Immediate or literal Add R4, R2, #3 R4 <- R4 + 3 for constants; 50% of ALU operations, 85% of compares; most values small Displacement or based LW R4, 100(R1) R4 <- M[100 + R1] used for accessing local variables; choosing length of displacement field affects instruction length Register deferred: use displacement mode with displacement = 0 (i.e., register holds a pointer) Absolute: use displacement mode with base register R0 (tied to 0) (i.e., directly address memory) · Branch addressing modes: PC relative and register indirect PC-relative branching Target is often near current instruction Use fewer bits to specify Position independence: permits code to run independently of where it is loaded Useful when target of branch is known at compile time (if not, can't use PC-rel) · Fixed instruction lengths · Few addressing modes & combinations; include addressing mode information as part of opcode Example: may have ADD and ADDI instructions; ADD: expects to see two register operands ADDI: expects second operand to be an immediate value, will decode accordingly 3. Operations: 4 classes (a) Loads and stores Only one addressing mode: base register plus 16-bit signed offset Example: LW R1, 30(R2) <<== R1 <- M[30 + R2] (loads 32-bit word) LW R1, 1000(R0) <<== R1 <- M[1000 + R0] (gives absolute address) Note: to load an immediate value into a register, use an ADDI with operand R0 and immediate (b) ALU operations (ADD, SUB, MUL, AND, OR, Shift, Compares) Usually have two source register operands and one register destination operand Example: ADD R2, R1, R3 <<== R2<-R1 + R3 Also, allow immediate operands Example: ADD R1, R2, #3 <<== R1<-R2+3 Compares (<, >, <=, >=, ==, !=) on two registers; if true, puts 1 in destination register; else 0 Example: SLT R1, R2, R3 <<== if (R2<$3) then R1<-1 else R1<-0 (c) Control instructions: branches and jumps Jumps are unconditional; either (1) specify 26-bit offset added to PC or (2) specify register with destination address; also jump and link (for procedure call), puts return address in R31 Example: J name <<== PC <- name Example: JALR R2 <<== R31 <-PC + 4; PC<-R2 (save PC+4 for return) Branches are conditional; test register source for equal to zero or not equal to zero Example: BNEZ R4, name <<== if (R4 != 0) then PC <- name; (16-bit offset) (d) Floating point operations (ADD, SUB, Mult, DIV, compares) Single or double precision; can convert between the two Example: ADDF F2, F3, F4 <<== F2 <- F3 + F4 4. Definition of register set 32 32-bit general purpose registers R0 is always 0 R31 holds the return addres of a procedure call 32 32-bit floating point registers: 32 single precision or 16 double-precision; double-precision registers accessed by even names (F0, F2,...) 32-bit program counter · Instruction format : 6 bits (up to 64 different opcodes) 1. I-Type (For loads, stores, immediates, conditional branch instructions, jump register) 2. R-Type (For register-register ALU operations) 3. J-Type (For jumps and Jump-and-link)