memory[0]=-1945632759
memory[1]=-1945829366
memory[2]=11022370
memory[3]=547553284
memory[4]=811925752
memory[5]=11020320
memory[6]=-1408958453
memory[7]=201326592
memory[8]=67108864
memory[9]=-1
memory[10]=4
memory[11]=0
@@@
state before cycle 0 starts
	pc 0
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction noop
		pcPlus1 0
	IDEX:
		instruction noop
		pcPlus1 0
		readRegA 0
		readRegB 0
		immediate 0
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 1 starts
	pc 1
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction lw 0 8 9
		pcPlus1 1
	IDEX:
		instruction noop
		pcPlus1 0
		readRegA 0
		readRegB 0
		immediate 0
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 2 starts
	pc 2
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction lw 0 5 10
		pcPlus1 2
	IDEX:
		instruction lw 0 8 9
		pcPlus1 1
		readRegA 0
		readRegB 0
		immediate 9
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 3 starts
	pc 3
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction sub 5 8 6 
		pcPlus1 3
	IDEX:
		instruction lw 0 5 10
		pcPlus1 2
		readRegA 0
		readRegB 0
		immediate 10
	EXMEM:
		instruction lw 0 8 9
		branchTarget 0
		branchCond 0
		aluOutput 9
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 4 starts
	pc 3
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction sub 5 8 6 
		pcPlus1 3
	IDEX:
		instruction noop
		pcPlus1 3
		readRegA 0
		readRegB 0
		immediate 12322
	EXMEM:
		instruction lw 0 5 10
		branchTarget 0
		branchCond 0
		aluOutput 10
		readRegB 0
	MEMWB:
		instruction lw 0 8 9
		loadMemData -1
		aluOutput 9
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 5 starts
	pc 4
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction addi 5 3 4
		pcPlus1 4
	IDEX:
		instruction sub 5 8 6 
		pcPlus1 3
		readRegA 0
		readRegB 0
		immediate 12322
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction lw 0 5 10
		loadMemData 4
		aluOutput 10
	WBEND:
		instruction lw 0 8 9
		writeRegData -1
@@@
state before cycle 6 starts
	pc 5
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 4
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction andi 3 5 248
		pcPlus1 5
	IDEX:
		instruction addi 5 3 4
		pcPlus1 4
		readRegA 0
		readRegB 0
		immediate 4
	EXMEM:
		instruction sub 5 8 6 
		branchTarget 0
		branchCond 0
		aluOutput 5
		readRegB -1
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction lw 0 5 10
		writeRegData 4
@@@
state before cycle 7 starts
	pc 6
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 4
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction add 5 8 5 
		pcPlus1 6
	IDEX:
		instruction andi 3 5 248
		pcPlus1 5
		readRegA 0
		readRegB 4
		immediate 248
	EXMEM:
		instruction addi 5 3 4
		branchTarget 0
		branchCond 0
		aluOutput 8
		readRegB 0
	MEMWB:
		instruction sub 5 8 6 
		loadMemData 0
		aluOutput 5
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 8 starts
	pc 7
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 4
		reg[ 6 ] 5
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction sw 0 5 11
		pcPlus1 7
	IDEX:
		instruction add 5 8 5 
		pcPlus1 6
		readRegA 4
		readRegB -1
		immediate 10272
	EXMEM:
		instruction andi 3 5 248
		branchTarget 0
		branchCond 0
		aluOutput 8
		readRegB 4
	MEMWB:
		instruction addi 5 3 4
		loadMemData 0
		aluOutput 8
	WBEND:
		instruction sub 5 8 6 
		writeRegData 5
@@@
state before cycle 9 starts
	pc 8
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 8
		reg[ 4 ] 0
		reg[ 5 ] 4
		reg[ 6 ] 5
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction noop
		pcPlus1 8
	IDEX:
		instruction sw 0 5 11
		pcPlus1 7
		readRegA 0
		readRegB 4
		immediate 11
	EXMEM:
		instruction add 5 8 5 
		branchTarget 0
		branchCond 0
		aluOutput 7
		readRegB -1
	MEMWB:
		instruction andi 3 5 248
		loadMemData 0
		aluOutput 8
	WBEND:
		instruction addi 5 3 4
		writeRegData 8
@@@
state before cycle 10 starts
	pc 9
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 0
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 8
		reg[ 4 ] 0
		reg[ 5 ] 8
		reg[ 6 ] 5
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction halt
		pcPlus1 9
	IDEX:
		instruction noop
		pcPlus1 8
		readRegA 0
		readRegB 0
		immediate 0
	EXMEM:
		instruction sw 0 5 11
		branchTarget 0
		branchCond 0
		aluOutput 11
		readRegB 7
	MEMWB:
		instruction add 5 8 5 
		loadMemData 0
		aluOutput 7
	WBEND:
		instruction andi 3 5 248
		writeRegData 8
@@@
state before cycle 11 starts
	pc 10
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 7
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 8
		reg[ 4 ] 0
		reg[ 5 ] 7
		reg[ 6 ] 5
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction data -1
		pcPlus1 10
	IDEX:
		instruction halt
		pcPlus1 9
		readRegA 0
		readRegB 0
		immediate 0
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction sw 0 5 11
		loadMemData 0
		aluOutput 11
	WBEND:
		instruction add 5 8 5 
		writeRegData 7
@@@
state before cycle 12 starts
	pc 11
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 7
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 8
		reg[ 4 ] 0
		reg[ 5 ] 7
		reg[ 6 ] 5
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction alu 0 0 0 
		pcPlus1 11
	IDEX:
		instruction data -1
		pcPlus1 10
		readRegA 0
		readRegB 0
		immediate -1
	EXMEM:
		instruction halt
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction sw 0 5 11
		writeRegData 0
@@@
state before cycle 13 starts
	pc 12
	data memory:
		dataMem[ 0 ] -1945632759
		dataMem[ 1 ] -1945829366
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 547553284
		dataMem[ 4 ] 811925752
		dataMem[ 5 ] 11020320
		dataMem[ 6 ] -1408958453
		dataMem[ 7 ] 201326592
		dataMem[ 8 ] 67108864
		dataMem[ 9 ] -1
		dataMem[ 10 ] 4
		dataMem[ 11 ] 7
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 8
		reg[ 4 ] 0
		reg[ 5 ] 7
		reg[ 6 ] 5
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction alu 0 0 0 
		pcPlus1 12
	IDEX:
		instruction alu 0 0 0 
		pcPlus1 11
		readRegA 0
		readRegB 0
		immediate 4
	EXMEM:
		instruction data -1
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction halt
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
machine halted
total of 13 cycles executed