memory[0]=-1945632764
memory[1]=-1945829371
memory[2]=11022370
memory[3]=67108864
memory[4]=-1
memory[5]=4
@@@
state before cycle 0 starts
	pc 0
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction noop
		pcPlus1 0
	IDEX:
		instruction noop
		pcPlus1 0
		readRegA 0
		readRegB 0
		immediate 0
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 1 starts
	pc 1
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction lw 0 8 4
		pcPlus1 1
	IDEX:
		instruction noop
		pcPlus1 0
		readRegA 0
		readRegB 0
		immediate 0
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 2 starts
	pc 2
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction lw 0 5 5
		pcPlus1 2
	IDEX:
		instruction lw 0 8 4
		pcPlus1 1
		readRegA 0
		readRegB 0
		immediate 4
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 3 starts
	pc 3
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction sub 5 8 6 
		pcPlus1 3
	IDEX:
		instruction lw 0 5 5
		pcPlus1 2
		readRegA 0
		readRegB 0
		immediate 5
	EXMEM:
		instruction lw 0 8 4
		branchTarget 0
		branchCond 0
		aluOutput 4
		readRegB 0
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 4 starts
	pc 3
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] 0
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction sub 5 8 6 
		pcPlus1 3
	IDEX:
		instruction noop
		pcPlus1 3
		readRegA 0
		readRegB 0
		immediate 12322
	EXMEM:
		instruction lw 0 5 5
		branchTarget 0
		branchCond 0
		aluOutput 5
		readRegB 0
	MEMWB:
		instruction lw 0 8 4
		loadMemData -1
		aluOutput 4
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 5 starts
	pc 4
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction halt
		pcPlus1 4
	IDEX:
		instruction sub 5 8 6 
		pcPlus1 3
		readRegA 0
		readRegB 0
		immediate 12322
	EXMEM:
		instruction noop
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction lw 0 5 5
		loadMemData 4
		aluOutput 5
	WBEND:
		instruction lw 0 8 4
		writeRegData -1
@@@
state before cycle 6 starts
	pc 5
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 4
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction data -1
		pcPlus1 5
	IDEX:
		instruction halt
		pcPlus1 4
		readRegA 0
		readRegB 0
		immediate 0
	EXMEM:
		instruction sub 5 8 6 
		branchTarget 0
		branchCond 0
		aluOutput 5
		readRegB -1
	MEMWB:
		instruction noop
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction lw 0 5 5
		writeRegData 4
@@@
state before cycle 7 starts
	pc 6
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 4
		reg[ 6 ] 0
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction alu 0 0 0 
		pcPlus1 6
	IDEX:
		instruction data -1
		pcPlus1 5
		readRegA 0
		readRegB 0
		immediate -1
	EXMEM:
		instruction halt
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction sub 5 8 6 
		loadMemData 0
		aluOutput 5
	WBEND:
		instruction noop
		writeRegData 0
@@@
state before cycle 8 starts
	pc 7
	data memory:
		dataMem[ 0 ] -1945632764
		dataMem[ 1 ] -1945829371
		dataMem[ 2 ] 11022370
		dataMem[ 3 ] 67108864
		dataMem[ 4 ] -1
		dataMem[ 5 ] 4
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 4
		reg[ 6 ] 5
		reg[ 7 ] 0
		reg[ 8 ] -1
		reg[ 9 ] 0
		reg[ 10 ] 0
		reg[ 11 ] 0
		reg[ 12 ] 0
		reg[ 13 ] 0
		reg[ 14 ] 0
		reg[ 15 ] 0
		reg[ 16 ] 0
		reg[ 17 ] 0
		reg[ 18 ] 0
		reg[ 19 ] 0
		reg[ 20 ] 0
		reg[ 21 ] 0
		reg[ 22 ] 0
		reg[ 23 ] 0
		reg[ 24 ] 0
		reg[ 25 ] 0
		reg[ 26 ] 0
		reg[ 27 ] 0
		reg[ 28 ] 0
		reg[ 29 ] 0
		reg[ 30 ] 0
		reg[ 31 ] 0
	IFID:
		instruction alu 0 0 0 
		pcPlus1 7
	IDEX:
		instruction alu 0 0 0 
		pcPlus1 6
		readRegA 0
		readRegB 0
		immediate 4
	EXMEM:
		instruction data -1
		branchTarget 0
		branchCond 0
		aluOutput 0
		readRegB 0
	MEMWB:
		instruction halt
		loadMemData 0
		aluOutput 0
	WBEND:
		instruction sub 5 8 6 
		writeRegData 5
machine halted
total of 8 cycles executed