ECE 438           Fall 2003

Homework Set 6

Due: Thursday, December 4th

NOTE: You may work as a group on this homework problem. Each group
should turn in only one group report with all group members names
listed. 


For this homework, you will experiment with the design of a cache
system for a hypothetical processor, using the data you will obtain
from the dinero cache simulator. Dinero simulates a wide variety of
cache configurations, which can be specified on its command line when
it is run. It works by reading in a trace of the sequence of address
references generated by a MIPS CPU simulator running a real program
compiled using a version of gcc designed to generate MIPS code. These
traces specify whether or not the memory transaction is an instruction
fetch, a data read (LOAD), or a data write (STORE). For each
transaction, dinero simulates the behavior of the type of cache you
have specified, generating hits and misses as appropriate. At the end
of the simulation, it produces a set of statistics summarizing the
performance of the simulation, including the total number of
transactions of each type, the percentage of misses in each case, and
the total amount of memory traffic generated for each type of
transaction, both in absolute terms and as a percentage of the total
amount of memory traffic generated by the CPU.

The class web page has links to a number of useful items for the
homework. The trace-based cache simulator, Dinero IV, is available in
source code or as a binary for Solaris (usable on the Sun workstations
in the student computer lab, room 211). The source code also compiles
on any UNIX system (e.g., Linux, SGI, IBM, etc.).

You will not have to generate your own trace files, that has been done
for you. Traces for 1-million instructions of three programs, cc1 (C
compiler), spice (a circuit simulator), and tex (a document formatter)
are available on the class webpage.

To run the dineroIV Solaris binary, save it from the web site and make
it executable ("chmod 755 dineroIV").  You can then execute it as

   dineroIV [cache options] < tracefile 

You can get command-line help for DineroIV by running "dineroIV
-help". The detailed manual page is available on the class web page.

Note that the tracefiles are in "traditional din" format, so use the
cache option "-informat d" for this homework.

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1. Use the dinero cache simulator to evaluate different instruction
and data cache sizes and block sizes for the following four different
workloads.  First, assume you will only use one of the three programs
on the machine all the time (that gives three different workloads, one
for a secretary using tex all the time, one for a circuit designer
using spice all the time, and one for a programmer using cc1 all the
time). Next, assume your workload consists of equal numbers of runs of
each of the three programs.

Simulate using both instruction and data cache sizes of 1K, 2K, 4k, 8k
and 16K (instruction and data cache size should be the same for each
simulation run).  Use block sizes of 8, 16, 32 and 64 bytes for each
of the instruction and data cache size combinations (A total of 20
combinations). Use default dinero parameters for rest of the cache
configurations. (Altogether, this is 4 workloads * 20 cache
combinations = 80 simulation runs.)

(1) Report the simulation results in table format. 

(2) Plot the results of the simulations in a graph showing the total
number of misses and total memory traffic for the different cache
configurations. Which configuration shows the least number of misses
and the least memory traffic.  

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2. Use the dinero cache simulator to evaluate associativity of cache 
blocks for each of the four different workloads.

Use block size of 32 bytes, unified cache size of 16K for all your
simulations. Simulate using set associativity of 1 (direct-mapped), 2,
4, 8. Use LRU and Random replacement policies for your simulations
(total of 8 combinations). Use write-through cache for all your
simulations. 

(1) Report the simulation results in table format. 

(2) Plot the results of the simulations in a graph showing the number
    of instruction, data, read and write misses and total memory traffic
    for the different cache configurations for each workload. Which
    configuration shows the least number of instruction, data, read
    and write misses and the least memory traffic.

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