Graduate Research Assistantship positions for M.S. and Ph.D. students
are available in the areas of parallel and multicore algorithms,
high-performance computing, computational science and engineering,
large-scale optimization problems, and in application area of
computational biology and genomics. Several current projects are
described below. Additional new projects are anticipated by the next
Fall semester. Each research assistant will receive a competitive
stipend plus paid tuition.
Applicants should complete an official application for graduate
studies in either the "Computational Science and Engineering (Computer Science)" or the "Computer Science" graduate programs at Georgia Tech,
and select the Computational Science and Engineering track. APPLICATION DEADLINE: December 15.
The Georgia Tech graduate application is available
online at http://www.gradadmiss.gatech.edu/
On Page 1, question 14 (Program of Study), of the online application,
select "GT-Atlanta" for the planned campus and either "Computational Science and Engineering (Computer Science)" or "Computer Science"
for Graduate Major.
One Page 4 (Georgia Tech department specific application page), question 1, select "Computational Science and Engineering" as your first choice area of interest.
In your statement on Page 4, please include this sentence:
"I wish to be considered for a Graduate Research Assistantship
under the direction of Professor David A. Bader."
Please email Prof. David A. Bader (
)
with your
First and Last name once you have submitted your online
application and received an Order ID.
PROJECT 1: Design and optimizing of multicore parallel algorithms
using the IBM-Sony-Toshiba CELL Processor
(Funded by IBM Research and Sony Corp.)
IBM, Sony, and Toshiba, have designed a new heterogeneous multicore
processor called "CELL" that is used in the Sony PlayStation 3 and
in IBM BladeServers. Georgia Tech is one of the first universities
in the world with Cell processors, in a shared research project
with IBM: an IBM BladeCenter with 4 Cell processors, each a 3.2GHz
processor with 1 GB RAM, running Linux. The challenge for Cell is
parallel programming of the main processor and its 8 synergistic
co-processors. In this project, we are challenged with designing
multicore parallel algorithms for optimized open source libraries
that run on Cell, such as FFT (www.fftw.org), ZLIB, and MPEG-2. A
Cell simulator, SDK, and example codes, are available from IBM
AlphaWorks. Students on the project will have access to the Cell
chip designers, performance engineers, and application developers,
at IBM, Sony, and Toshiba!
PROJECT 2: Design Efficient Parallel Algorithms for Multi-Core Processors
(Funded by Microsoft Research)
Since the inception of the desktop computer, performance of
software has improved at an exponential rate, primarily driven by
the steady technological improvements of microprocessors. Due to
fundamental physical limitations and power constraints, we are now
witnessing a radical change in commodity microprocessor
architecture, to multi-core designs. Continued performance now
requires the exploitation of concurrency at the algorithmic
level. We propose to design a parallel programming methodology for
client systems with commodity multi-core processors by providing a
productive, easy-to-use portable library package called SWARM
(SoftWare and Algorithms for Running on Multicore). In this
project, we will design and optimize a portable and efficient
library of basic primitives that fully exploit multi-core
processors.
Graph abstractions are used in many computationally challenging
science and engineering problems; for instance, in VLSI layout,
data mining, wireless communication and distributed networks,
clustering in semantic webs, recent problems in biology and
medicine such as cancer detection, medical imaging, protein
function determination, and national security and bioterrorism such
as detecting the spread of toxins through populations in the case
of biological/chemical warfare. These graphs may contain billions
of vertices with degrees ranging from small constants to thousands.
There are plenty of theoretically fast parallel algorithms for
graph problems in the literature, e.g., work-time optimal PRAM
algorithms and communication-optimal BSP algorithms; however, in
practice there are seldom any parallel implementations that beat
the best sequential implementations for arbitrary, sparse graphs.
This project focuses on parallel algorithm design and engineering
techniques that better fit current and future architectures and
obtain high performance implementations for solving real-world
problems.
PROJECT 4: Design Optimization Frameworks for High-Productivity Computing
(Funded by the National Science Foundation)
High-performance computing (HPC) systems are taking a revolutionary
step forward with complex architectural designs that require
application programmers and compiler writers to perform the
challenging task of optimizing the computation in order to achieve
high performance. Realizing the gap between processor and memory
performance, several leading HPC vendors plan to incorporate into
their next-generation systems innovative architectural features
that alleviate this memory wall. These new architectural features
include hardware accelerators (e.g., reconfigurable logic such as
FPGAs, SIMD/vector processing units such as in IBM Cell, and
graphics processing units (GPUs)), adaptable general-purpose
processors, run-time performance advisors, capabilities for
processing in the memory subsystem, and power optimizations. With
these innovations, the multidimensional design space for optimizing
applications is huge. Software must be sensitive to data layout,
cache parameters, and data reuse, as well as dynamically changing
resources, for highest performance. Our research goal is to design
a dynamic application composition system that provides both a
framework for optimizing computational science and engineering
applications and their high-performance computing technologies and
increased productivity.
