Cache hardware in a typical set-associative cache consumes a non-trivial amount of transistors -- and consequently power -- compared to the same amount of plain SRAM. Using dynamic binary translation we simulate a fully-associative cache using a regular SRAM array. Full associativity provides some real-time guarantees about miss rates and a more application-writer-friendly programming model. Removing the caching hardware (i.e., tags, comparators, and the associated wires) can also reduce the power consumed by the cache.

Software Bubbling is a technique that allows aggressive scheduling of loops bodies which may contain aliasing. Using the predication features available in some modern processors, the loop is scheduled assuming there is no aliasing. At runtime, when the actual values of possible aliased addresses are known, we check for aliasing. If there is no aliasing, then the aggressive loop body is executed; if there is aliasing, then the instructions in the loop are predicated in such a way that the loop can be executed safely.