Buzzword ISA microarchitecture fixed length vs. variable length architectural state control instructions datapath fetch stage decode stage execution stage write back stage CDB (Common Data Bus) cache line cache block prefetch store buffer interrupt exception trace cache pipelining pipeline latches scoreboard data forwarding control dependency data dependency output dependency anti dependency true dependency name dependency Tomasulo’s algorithm Architecture registers Register renaming Physical registers Out-of-order execution In-order execution Register alias table Reservation stations Out of order completion Branch prediction Delayed branch Delay slot Compile-time branch prediction Run-time branch prediction BTFN Last time predictor Suturing two-bit counter predictor Two-level branch predictor Global branch predictor Branch history register Global history Pattern history table Moore’s law Benchmarks Statistical simulation Trace driven simulation Execution driven simulation GFLOPS MIPS IPC Performance Throughput CPI Arithmetic mean Weighed arithmetic mean Geometric mean ILP (Instruction level parallelism) TLP (Thread level parallelism) Superscalar Bandwidth Issue width Data dependencies Control dependencies Memory dependencies RAW/WAR/WAW Hazards ILP Multicycle stages Forwarding paths Broadcasting Dynamic scheduling History buffer Check point Misprediction Indirect branch Return address stack BTB (Branch Target Buffer) Tournament Predictor Spatial locality Temporal locality Cache replacement policy Cache write policy Direct mapped cache Fully associative cache Set-associative cache Valid bit Tag bit FIFO replacement LRU replacement Pseudo LRU replacement Write-allocation No-write-allocation Write-through Write-back Dirty bit Interleaving AMAT (average memory access time) Memory level parallelism Exclusion property Inclusion property Early restart (in cache) Critical first ( in cache) Merging write buffers Compulsory, capacity, conflict misses Larger block Higher associativity Loop interchange Virtual index physical tag Pipelined cache Trace cache MSHR (Miss status /information Holding Register) Way prediction Non-blocking cache Prefetching Virtual memory TLB Multi-level page tables VIPT cache VIVT cache PAPT (PIPT) cache Virtual memory Physical Page Physical Frame Virtual Page Page Table ----------------- DRAM/SRAM Row-buffer Dram page Destructive read Refresh Burst length Memory controller Bandwidth Channel Rank Bank