FAQ

How do I update PC value in the simulator?

I didn't modify my code at all and it generates "ERROR! OP_POOL SIZE is too small!! ".!!

I get "NO_OP_TYPE" assertion. What did I do wrong?

You might have not corrected your code. (sim_end_condition)
You might be running your code on different gcc version or 32-bit. Please check your code in killerbee machines
You might be doing something wrong with your op pointers.

When there is a branch instruction, when can the front-end start to fetch a new instruction from the correct path?

When to update data hazard and control hazard?

Whenever a pipeline is stalled due to data dependences and control dependences, you increment the corresponding counters in the ID stage

The same instruction can increment both data hazard counter and control hazard counter.
If one instruction has two data dependences (i.e., both source operands are dependent on other instructions), data hazard counter is only incremented by one.
If the same instruction needs to wait for several cycles in the ID stage due to long latency operations, you still increment the data hazard counter multiple cycles. (i.e., while an instruction is waiting in the ID stage, the data hazard counter is continuously incremented. ) To simplify the hardware counter design, you can increment the control hazard counter multiple times, if a branch instruction is waiting in the ID stage.

Do I need to implement sim_end_condition?

Yes, you must implement sim_end_condition.
The success variable at "success = (gzread(stream, &trace_op, sizeof(Trace_op)) > 0 );" tells the end of trace. If the success value is false, it means the end of trace. When the trace reaches the end, you must send an op that indicates the end of trace by using some conditions such as (op->last_op = TRUE). If that op reaches WB_stage, the simulator sets sim_end_condition as TRUE.
Note that last_op field is not provided in the simulator frame. You must add such kind of field.

I cannot access killerbee1.cc.gatech.edu

Please contact TSO. All CS graduate students should have access to all killerbee machines

Do I need to understand all the files?

Please focus on sim.cpp sim.h file. trace.cpp is to generate traces and sim_pin.cpp is for pin interface.

What is Op_pool?

To avoid of calling malloc all the time, op structures are already created.

What is the difference between max_insts and max_cycles knob?

max_insts: a simulation ends after executing max_insts number of instructions.
max_cycles: a simulation ends after executing max_cycles number of cycles.

How do we handle instructions that take multiple cycles?

How can we check a branch instruction?

if ((op->cf_type) >= CF_BR)

Do we need to differentiate branch types?

No. All branches are treated equally in this assignment.

Do we need to use dcache_access, icache_access functions?

No, you don't need to use them.

Why are there op_arrays? instead of just one Op?

We used op_arrays for future assignments. To build a superscalar processor.

Do store instructions also write to register files?

Yes, Store instructions can write the register files.

Can I use write_flg to check whether an instruction writes a value to a register file or not?

No, write_flg is for EFLAGS in x86. You need to check op->dst to see whether there is a write access or not. if op->dst is "-1", the instruction does not write to a register file.