CS7290 Advanced microarchitecture
Fall 2014
Instructor: Prof. Hyesoon Kim
Due: November 7 (Friday) 6 pm
Overview:
In this assignment, you extend your processor design (proj2)
to handle variable memory latency and support out-of-order execution.
Instead of building your own cache, we provide a multi-latency memory system. Please see the example
and connect the memory system in your pipeline design.
You can do this project with another student in the class. A group project
For the instruction cache, we still keep the same SRAM based accesses. Only data load operations
are using the memory model.
A simple assembler is provided to help your project.
What to submit
- Report:
- Diagram: Pipeline design diagram
- Screenshots of the waveforms. Please show whether you handle branch and data dependence correctly in the screenshots.
- You should clearly show whether the pipeline is correctly executed using the screen shot.
- all your source code.
please tar your all files and submit them as proj4.tar
Note: We only grade based on your report. The source code might be used to check
your implementation.
Please write multiple test applications to demonstrate your functionality.
Grading policy:
- (40 points) Integrating the pipeline and the latency memory module (blocking memory system)
- (50 points) Implementation of Out-of-order execution
- (10 points) Report discussion.
- (20 points) (extra) Non-blocking memory system. You need a MSHR like structure to handle the non-blocking memory system.
Since project #4 is significantly longer than other projects, the weight factor for this assignment is 1.5.
Here is the testing assembly code