Publications by Date
Publications by Topics

  • Topics
  • Heterogeneous Architectures
    • Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture," In Journal of Parallel and Distributed Computing (JPDC), Vol. 73, Issue 12, pp. 1525-1538, December 2013

    • Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Adaptive Virtual Channel Partitioning for Network-on-Chip in Heterogeneous Architectures," In ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, pp.48:1-48:28, October 2013

    • Jieun Lim, Hyesoon Kim,
      "Design Space Exploration of Memory Model for Heterogeneous Computing,"
      ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC-2012) in conjunction with PLDI, Beijing, China, June 2012 (poster).

    • Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili, "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Architecture", GIT-CERCS-12-05, Georgia Institute of Technology, 2012.

    • Jaekyu Lee and Hyesoon Kim,
      "TLP-Aware Cache Management Schemes for a CPU-GPU Heterogeneous Architecture",
      Proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA), New Orleans, LA, February 2012

    • Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin,
      "DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function",
      IEEE Computer Architecture Letters (CAL), Nov. 2011

    • Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim "Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping," MICRO 2009 , December, 2009.

  • Graphics Processing Units (GPUs)
    • Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William Song, Sudhakar Yalamanchili, and Wonyong Sung,   "Power Modeling for GPU Architectures Using McPAT," ACM Trans. Des. Autom. Electron. Syst. 19, 3, Article 26 (June 2014)

    • Nagesh B Lakshminarayana, Hyesoon Kim, "Spare Register Aware Prefetching for Graph Algorithms on GPUs, "HPCA 2014

    • Jen-Cheng Huang, Lifeng Nai, Hyesoon Kim, Hsien-Hsin Lee, "TBPoint: Reducing Simulation Time for Large Scale GPGPU Kernels," IPDPS 2014, May 2014

    • Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture," In Journal of Parallel and Distributed Computing (JPDC), Vol. 73, Issue 12, pp. 1525-1538, December 2013

    • Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Adaptive Virtual Channel Partitioning for Network-on-Chip in Heterogeneous Architectures," In ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, pp.48:1-48:28, October 2013

    • Joo Hwan Lee, Jiayuan Meng, Hyesoon Kim, "SESH framework: A Space Exploration Framework for GPU Application and Hardware Codesign," 4th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS13), held as part of SC13, Denver, Colorado, USA, November 2013

    • Hyesoon Kim,
      "Supporting Virtual Memory in GPGPU without Supporting Precise Exceptions,"
      ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC-2012) in conjunction with PLDI, Beijing, China, June 2012(poster).

    • Jae Woong Sim, Aniruddha Dasgupta, Hyesoon Kim, and Richard Vuduc,
      "A Performance Analysis Framework for Identifying Performance Benefits in GPGPU Applications",
      Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New Orleans, LA, February 2012

    • Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin,
      "DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function",
      IEEE Computer Architecture Letters (CAL), Nov. 2011

    • Dongwon Lee, Marilyn Wolf, Hyesoon Kim, "Design Space Exploration of the Turbo Decoding Algorithm on GPUs," CASES, Oct. 2010.

    • Sunpyo Hong, Hyesoon Kim, "An Integrated GPU Power and Performance Model," ISCA-37, June 2010.

    • Nagesh B. Lakshminarayana, Hyesoon Kim "Effect of Instruction Fetch and Memory Scheduling on GPU Performance," Workshop on Language, Compiler, and Architecture Support for GPGPU, in conjunction with HPCA/PPoPP 2010, 2010.

    • Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim "Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping," MICRO 2009 , December, 2009.

    • Sunpyo Hong, Hyesoon Kim, "An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness," Proceedings of the 36th International Symposium on Computer Architecture (ISCA) , Austin, TX, June 2009.

  • Tools to help Parallel Programming
  • Memory Systems
  • Power
  • Profiling
    • Joo Hwan Lee, Jiayuan Meng, Hyesoon Kim, "SESH framework: A Space Exploration Framework for GPU Application and Hardware Codesign," 4th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS13), held as part of SC13, Denver, Colorado, USA, November 2013

    • Bevin Brett, Pranith Kumar, Minjang Kim, Hyesoon Kim, "CHiP: A Profiler to Measure the effect of Cache Contention on Scalability," Workshop on Multithreaded Architectures and Applications in conjunction with IPDPS-27, Boston, USA, May 2013

    • Joo Hwan Lee, Kaushik Patel, Nimit Nigania, Hyojong Kim, Hyesoon Kim, "OpenCL Performance Evaluation on Modern Multi Core CPUs," Multicore and GPU Programming Models, Languages and Compilers Workshop(PLC 2013), in conjunction with IPDPS-27, Boston, USA, May 2013
    • Minjang Kim, Hyesoon Kim, Chi-Keung Luk, "SD3: A scalable Approach to Data-Dependence Profiling ," MICRO-43, Atlanta, GA, 2010.

    • Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
      "2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set,"
      Proceedings of the 4th International Symposium on Code Generation and Optimization (CGO), pages 159-169, New York, NY, March 2006.
      An extended version as HPS Technical Report, TR-HPS-2006-001, University of Texas at Austin, January 2006.

  • Mobile computing
  • Simulator
    • Jen-Cheng Huang, Lifeng Nai, Hyesoon Kim, Hsien-Hsin Lee, "TBPoint: Reducing Simulation Time for Large Scale GPGPU Kernels," IPDPS 2014
      May 2014
    • Arun Rodrigues, Keren Bergman, David Bunde, Elliott Cooper-Balis, Kurt Ferreira, Scott Hemmert, Brian Barrett, Robert Hendry, Bruce Jacob, Hyesoon Kim, Vitus Leung, Michael Levenhagen, Mitchelle Rasquinha, Rolf Riesen, Paul Rosenfeld, Maria Del Carmen Ruiz Varela, Sudhakar Yalamanchili and Cassandra Versaggi,
      "Improvements to the Structural Simulation Toolkit,"
      5th International ICST Conference on Simulation Tools and Techniques (SIMUtools 2012), Desenzano, Italy, Mar. 2012.

  • Thread scheduling
  • Reducing Branch Misprediction Penalty