Last time predictor 2 bits counter Gshare branch predictor Branch target buffer Return Address Stack Loop branch Predication Loop unrolling VLIW Heterogeneous architecture PPE/SPE DMA Static instruction scheduling Even pipe/odd pipe DMA engine Instruction prefetch Coherent bus logic U-pipe/V-pipe Ring network Performance evaluations Benchmarks CPI/IPC Arithmetic mean Harmonic mean Frame rate Execution driven/trace-driven Thumb instruction decode 3 stage register read port Split transactions Amdahl’s law Memory wall Power wall