Reading List

• [XBOX1]Xbox 360 System Architecture, IEEE Micro, Vol. 26, No. 2, March-April 2006, pp. 25-37.
• [XBOX2] The XBOX 360 System Architecture, HotChips 2005, August 2005

• [HT] Hyper-Threading Technology Architecture and Microarchitecture, Marr, D.; Binns, F.; Hill, D.; Hinton, G.; Koufaty, D.; Miller, J.; Upton, M. Intel Technology Journal, Vol. 6, No. 1, Feb. 2002

• [SIMD2] Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU. Mauricio Breternitz Jr., Herbert Hum, Sanjeev Kumar. In the Proceedings of ACM/IEEE International Conference on Parallel Architecture and Compilation Techniques (PACT), New Orleans, Louisiana, September 2003.

• [PGH]Programming Graphics Hardware

• [CUDA1] CUDA 2.0 Programming Guide
• [CUDA2] CUDA 2.0 Reference Manual
• [CUDA3] Scalable parallel programming with CUDA, John Nickolls, Ian Buck, Michael Garland, Kevin Skadron, August 2008, SIGGRAPH '08: SIGGRAPH 2008 classes
• [TES] NVIDIA Tesla: A Unified Graphics and Computing Architecture, Lindholm, E.; Nickolls, J.; Oberman, S.; Montrym, J.; Micro, IEEE, Volume 28, Issue 2, March-April 2008 Page(s):39 - 55,

• [CELL1] Introduction to the Cell Multiprocessor
• [CELL2] Synergistic Processing in Cell's Multicore Architecture, IEEE Micro, Vol. 26, No. 2, March-April 2006, pp.10-24.
• [POWER5] IBM Power5 Chip: A Dual-Core Multithreaded Processor. Ronald N. Kalla, Balaram Sinharoy, and Joel M. Tendler. IEEE Micro. 24(2), 2004

• [RAY1] Real-Time Ray Tracing with CUDA

• [LRB] Larrabee: a many-core x86 architecture for visual computing, Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan, August 2008,SIGGRAPH '08: SIGGRAPH 2008 papers

• [ARM1] ARM946E-S ARM processor
• [ARM2] ARM7TDMI

• [WOR]Workload Characterization of 3D Games

• [DDR]DirectRambus

• [FP]IEEE Standard 754 for Binary Floating-Point Arithmetic