JAEKYU LEE
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As of February, 2012 [PDF]
Objective

To obtain a summer internship position in computer architecture, compiler, software development, and parallel computing.

Research Interests

High-performance computer architecture, high-performance computing

Education

Georgia Institute of Technology, Atlanta, GA

Ph.D. student in Computer Science, Fall 2009 ~ Present
M.S. in Computer Science, May 2009

Sogang University, Seoul, Korea

B.S. in Computer Science, February 2007

Work Experience

Georgia Institute of Technology, Graduate Research Assistant, Atlanta, GA, 2008 - Present

Graduate Research Assistant with Prof. Hyesoon Kim
  • Resource management in CPU-GPU heterogeneous architectures
    • Cache sharing mechanism in last-level cache [HPCA'12]
    • On-chip interconnection network [JETCAS'12 submitted]
  • GPGPU research
    • Many-thread aware hardware and software preetching [MICRO'10]
    • Memory scheduling [IEEE CAL]
  • Heterogeneous architecture simulator - main developer of MacSim simulator
    http://code.google.com/p/macsim
  • Software and hardware prefetching mechanisms and their interactions [TACO'12]
  • Thread scheduling on asymmetric multiprocessors [SC'09]
  • High performance parallel computing

Intel Corperation, Austin, TX, May 2011 - August 2011

Graduate Technical Intern in Visual and Parallel Computing Group (VPG)
Manager: Eric Sprangle

2nd Infantry Division, US Army, July 2004 - July 2006

Network Administrator as a KATUSA (Korean Augmented Troops to the US Army) during military service

Publications

  1. Jaewoong Sim, Jaekyu Lee, Moinnuddin Qureshi, and Hyesoon Kim
    "FLEXclusion: Balancing Cache Capacity and On-Chip Traffic with Flexible Exclusion"
    In Prof. of the 39th Int'l Symp. on Computer Architecture (ISCA-39),
    Portland, OR, June, 2012 (acceptance rate 18% (47/262)), to appear

  2. Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili
    "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Architecture",
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), submitted

  3. Jaekyu Lee, Hyesoon Kim, and Richard Vuduc,
    "When Prefetching Works, When It Doesn't, and Why"
    In ACM Transactions on Architecture and Code Optimization (TACO), Vol. 9, No. 1, pp.2:1-2:29, March, 2012

  4. Jaekyu Lee and Hyesoon Kim
    "TAP: A TLP-Aware Cache Management Schemes for a CPU-GPU Heterogeneous Architecture",
    In Proc. of the 18th Int'l Symp. on High Performance Computer Architecture (HPCA-18), pp.91-102
    New Orleans, LA, February, 2012 (acceptance rate 17% (36/210)) Slide

  5. Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin
    "DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function"
    IEEE Computer Architecture Letters (CAL), accepted

  6. Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, and Richard Vuduc,
    "Many-Thread Aware Prefetching Mechanisms for GPGPU Applications"
    In Proc. of the 43rd Int'l Symp. of Microarchitecture (MICRO-43), pp.213-224
    Atlanta, GA, December, 2010 (acceptance rate 18% (45/248)) Slide

  7. Nagesh B. Lakshminarayana, Jaekyu Lee, and Hyesoon Kim,
    "Age Based Scheduling for Asymmetric Multiprocessors"
    SC, pp.25:1-25:12, November, 2009 (acceptance rate 23% (59/261)) Slide

Talks

  1. HPCA-18, "MacSim simulator tutorial"

  2. HPCA-18, "TAP: A TLP-Aware Cache Management Polify for a CPU-GPU Heterogeneous Architecture"

  3. MICRO-43, "Many-Thread Aware Prefetching MEchanisms for GPGPU Applications"

Awards and Honors

10th place in ACM ICPC (International Collegiate Programming Contest) Asia Regional, Nov. 2003

Computer Skills

Language: C, C++, Perl, Python, CUDA, JAVA (J2SE, J2ME), Visual C++, Visual Basic, VHDL, JSP, Matlab

Operating System: Windows, Unix, Linux

Architecture Tools: PIN, PAPI, LLVM

Personal Information

Citizenship: Republic of Korea

Visa status: F1

Reference

Available upon requests