Gabriel H. Loh

Gabriel H. Loh
Publications

Grouped by Type
Grouped Chronologically

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	Book Chapters

1.	Gabriel H. Loh 3D Microprocessor Design In "Three Dimensional Integrated Circuits: EDA, Design and Microarchitecture", Jason Cong, Sachin Sapatnekar, Yuan Xie; Springer, 2009

2.	Gabriel H. Loh Advanced Instruction Flow Techniques In "Modern Processor Design: Fundamentals of Superscalar Processors", John Paul Shen and Mikko H. Lipasti; McGraw Hill, 2005


	Peer-Reviewed Conference Papers

1.	Yuejian Xie, Gabriel H. Loh Scalable Shared Cache Management by Containing Thrashing Workloads To appear in the International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC), January 25-27, 2010, Pisa, Italy.

2.	Gabriel H. Loh Extending the Effectiveness of 3D-Stacked DRAM Caches with an Adaptive Multi-Queue Policy (pdf) To appear in the International Symposium on Microarchitecture (MICRO), December 12-16, 2009, New York, NY, USA.

3.	Yuejian Xie, Gabriel H. Loh PIPP: Promotion/Insertion Pseudo-Partitioning of Multi-Core Shared Caches (pdf) In the International Symposium on Computer Architecture (ISCA), pp. 174-183, June 20-24, 2009, Austin, TX, USA.

4.	Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie Zesto: A Cycle-Level Simulator for Highly Detailed Microarchitecture Exploration (pdf) In the International Symposium on Performance Analysis of Software and Systems (ISPASS), pp. 53-64, April 27, 2009, Boston, MA, USA.

5.	Samantika Subramaniam, Anne C. Bracy, Hong Wang, Gabriel H. Loh Criticality-Based Optimizations for Efficient Load Processing. (pdf) In the 19th International Symposium on High-Performance Computer Architecture (HPCA), pp. 419-430, February 18, 2009, Raleigh, NC, USA.

6.	Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim Thermal Optimization in Multi-Granularity Multi-Core Floorplanning (pdf) In the 14th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 43-48, January 19, 2009, Yokohama, Japan.

Mauricio Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeffrey Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu
A Segmented Bloom Filter Algorithm for Efficient Predictors (pdf)
In the 20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp. 123-130, October 30, 2008, Campo Grande, Brazil.

8.	Gabriel H. Loh 3D-Stacked Memory Architectures for Multi-Core Processors (pdf) In the 35th ACM International Symposium on Computer Architecture (ISCA), pp. 453-464, June 21-25, 2008, Beijing, China.

9.	Gabriel H. Loh A Modular 3D Processor for Flexible Product Design and Technology Migration (pdf) In the ACM International Conference on Computing Frontiers (CF), pp. 159-170, May 5-7, 2008, Ischia, Italy.

10.	Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh PEEP: Exploiting Predictability of Memory Dependences in SMT Processors (pdf) In the 14th International Symposium on High-Performance Computer Architecture (HPCA), pp. 137-148, February 16-20, 2008, Salt Lake City, UT, USA.

11.	Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black Matrix Scheduler Reloaded (pdf) In the 34th International Symposium on Computer Architecture (ISCA), pp. 335-346, June 9-13, 2007, San Diego, CA, USA.

12.	Kiran Puttaswamy, Gabriel H. Loh Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors (pdf) In the ACM Design Automation Conference (DAC), pp. 622-625, June 4-8, 2007, San Diego, CA, USA.

13.	Kiran Puttaswamy, Gabriel H. Loh Thermal Herding: Microarchitecture Techniques for Controlling HotSpots in High-Performance 3D-Integrated Processors (pdf) In the 13th International Symposium on High-Performance Computer Architecture (HPCA), pp. 193-204, February 13, 2007, Phoenix, AZ, USA.

14.	Samantika Subramaniam, Gabriel H. Loh Fire-and-Forget: Load/Store Scheduling with No Store Queue at All (pdf) In the 39th International Symposium on Microarchitecture (MICRO), pp. 273-284, December 9-13, 2006, Orlando, FL, USA. *Best student presentation award*

15.	Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh Adaptive Caches: Effective Shaping of Cache Behavior to Workloads (pdf) In the 39th International Symposium on Microarchitecture (MICRO), pp. 385-396, December 9-13, 2006, Orlando, FL, USA.

16.

Bryan Black, Murali M. Annavaram, Edward Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCauley, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadas Shankar, John Paul Shen, Clair Webb
Die Stacking (3D) Microarchitecture (pdf)
In the 39th International Symposium on Microarchitecture (MICRO), pp. 469-479, December 9-13, 2006, Orlando, FL, USA.

17.	Chinnakrishnan Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee Entropy-based Low Power Data TLB Design (pdf) In the ACM/IEEE Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), pp. 304-311, October 23-25, 2006, Seoul, South Korea.

18.

Daniel A. Jimenez, Gabriel H. Loh
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors (pdf)
In the 18th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pp. 55-62, October 18, 2006, Ouro Preto, Brazil.

19.	Kiran Puttaswamy, Gabriel H. Loh Thermal Analysis of a 3D Die-Stacked High-Performance Microprocessor (pdf) In the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 19-24, May 1, 2006, Philadelphia, PA, USA.

20.	Kiran Puttaswamy, Gabriel H. Loh Dynamic Instruction Schedulers in a 3-Dimensional Integration Technology (pdf) In the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 153-158, May 1, 2006, Philadelphia, PA, USA.

21.	Kiran Puttaswamy, Gabriel H. Loh The Impact of 3-Dimensional Integration on the Design of Arithmetic Units (pdf) In the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4951-4954, May 24, 2006, Kos, Greece.

22.	Gabriel H. Loh Revisiting the Performance Impact of Branch Predictor Latencies (pdf) In the International Symposium on Performance Analysis of Software and Systems (ISPASS), pp. 59-69, March 20, 2006, Austin, TX, USA.

23.	Kiran Puttaswamy, Gabriel H. Loh Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology (pdf) In the IEEE International Symposium on VLSI (ISVLSI), pp. 384-389, March 3, 2006, Karlsrühe, Germany.

24.

Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh
Microarchitectural Floorplanning Under Performance and Temperature Tradeoff
In the Conference for Design, Automation and Test in Europe (DATE), pp. 1288-1293, March 9, 2006, Munich, Germany.

25.	Samantika Subramaniam, Gabriel H. Loh Store Vectors for Scalable Memory Dependence Prediction and Scheduling (pdf) In the 12th International Symposium on High-Performance Computer Architecture (HPCA), pp. 64-75, February 13, 2006, Austin, TX, USA. *Best student presentation award*

26.	Kiran Puttaswamy, Gabriel H. Loh Implementing Caches in a 3D Technology for High Performance Processors (pdf) In the International Conference on Computer Design (ICCD), pp. 525-532, October 5, 2005, San Jose, CA, USA.

27.	Gabriel H. Loh A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction (pdf) In the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 243-254, September 20, 2005, St. Louis, MO, USA.

28.	Peter G. Sassone, D. Scott Wills, Gabriel H. Loh Static Strands: Safely Collapsing Dependence Chains for Increasing Embedded Power Efficiency (pdf) In the Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), pp. 127-136, June 16, 2005, Chicago, IL, USA.

29.	Gabriel H. Loh Simulation Differences Between Academia and Industry: A Branch Prediction Case Study (pdf) In the International Symposium on Performance Analysis of Software and Systems (ISPASS), pp. 21-31, March 20, 2005, Austin, TX, USA.

30.	Gabriel H. Loh Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth (pdf) In the 35th International Symposium on Microarchitecture (MICRO), pp. 395-405, November 18-22, 2002, Istanbul, Turkey.

31.	Gabriel H. Loh, Dana S. Henry Predicting Conditional Branches With Fusion-Based Hybrid Predictors (pdf) In the 11th Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 165-176, September 22-25, 2002, Charlottesville, VA, USA.

32.	Gabriel H. Loh, Dana S. Henry Applying Machine Learning for Ensemble Branch Predictors (pdf) In the 15th Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems (IEAAIE), pp. 264-274, June 17-20, 2002, Cairns, Australia. Springer LNCS-2358.

33.	Dana S. Henry, Gabriel H. Loh, Rahul Sami Speculative Clustered Caches for Clustered Processors (pdf) In the 4th International Symposium on High Performance Computing (ISHPC), pp. 281-290, May 15-17, 2002, Kansai Science City, Japan. Springer LNCS-2327.

34.	Gabriel H. Loh A Time-Stamping Algorithm of Efficient Performance Estimation of Superscalar Processors (pdf) In the Joint International Conference on Measurement & Modeling of Computer Systems (SIGMETRICS), pp. 72-81, June 16-20, 2001, Cambridge, MA, USA.

35.	Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami Circuits for Wide-Window Superscalar Processors (pdf) In the 27th International Symposium on Computer Architecture (ISCA), pp. 236-247, June 10-14, 2000, Vancouver, Canada.

36.	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh A Comparison of Scalable Superscalar Processors (pdf) In the 11th Symposium on Parallel Algorithms and Architectures (SPAA), pp. 126-137, June 27-30, 1999, Saint-Malo, France. (Also appears in a journal version.)


	Peer-Reviewed Journal Articles

1.	Samantika Subramaniam, Gabriel H. Loh Design and Optimization of the Store Vectors Memory Dependence Predictor To appear in ACM Transactions on Architecture and Code Optimization (TACO).

2.	Kiran Puttaswamy, Gabriel H. Loh 3D-Integrated SRAM Components for High-Performance Microprocessors In the IEEE Transactions on Computers (TC), vol. 58(10), pp. 1369-1381, October, 2009.

3.	Gabriel H. Loh, Daniel A. Jimenez Modulo Path History for the Reduction of Pipeline Overheads in Path-Based Neural Branch Predictors In the Springer International Journal of Parallel Programming (IJPP), vol. 36(2), pp. 267-286, April, 2008.

4.	Peter G. Sassone, D. Scott Wills, Gabriel H. Loh Static Strands: Safely Exposing Dependence Chains for Increasing Embedded Power Efficiency (pdf) In ACM Transactions on Embedded Computing Systems (TECS), vol. 6(4), September, 2007.

5.	Gabriel H. Loh, Yuan Xie, Bryan Black Processor Design in Three-Dimensional Die-Stacking Technologies (pdf) In IEEE Micro, vol. 27(3), pp. 31-48, May-June, 2007.

6.	Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh Multi-Objective Microarchitectural Floorplanning for 2D and 3D ICs (pdf) In IEEE Transactions on Computer Aided Design (TCAD), vol. 26(1), pp. 38-52, January, 2007.

7.	Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein Design Space Exploration for 3D Architectures (pdf) In ACM Journal of Emerging Technologies in Computing Systems (JETC), vol. 2(2), pp. 65-103, April, 2006.

8.	Gabriel H. Loh Deconstructing the Frankenpredictor for Implementable Branch Predictors (pdf) In Journal of Instruction Level Parallelism (JILP), vol. 7, pp. 1-10, April, 2005.

9.	Gabriel H. Loh Width-Partitioned Load Value Predictors (pdf) In Journal of Instruction Level Parallelism (JILP), vol. 5, pp. 1-23, November, 2003.

10.	Gabriel H. Loh, Dana S. Henry, Arvind Krishnamurthy Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors (pdf) In Journal of Instruction Level Parallelism (JILP), vol. 5, pp. 1-32, June, 2003.

11.	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh A Comparison of Asymptotically Scalable Superscalar Processors (pdf) In Theory of Computing Systems, vol. 35(2), pp. 129-150, April 5, 2002, Springer-Verlag.


	Peer-Reviewed Workshop Papers

1.	Rahul Garde, Samantika Subramaniam, Gabriel H. Loh Deconstructing the Inefficacy of Global Cache Replacement Policies (pdf) In the 7th Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 22, 2008, Beijing, China. (Held in conjunction with ISCA-35.)

2.	Yuejian Xie, Gabriel H. Loh Dynamic Classification of Program Memory Behaviors in CMPs (pdf) In the 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), June 22, 2008, Beijing, China. (Held in conjunction with ISCA-35.)

3.	Jonathan D. Kron, Brooks Prumo, Gabriel H. Loh Double-DIP: Augmenting DIP with Adaptive Promotion Policies to Manage Shared L2 Caches (pdf) In the 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), June 22, 2008, Beijing, China. (Held in conjunction with ISCA-35.)

4.	Gabriel H. Loh The Cost of Uncore in Throughput-Oriented Many-Core Processors (pdf) In the Workshop on Architectures and Languages for Throughput Applications (ALTA), June 22, 2008, Beijing, China. (Held in conjunction with ISCA-35.)

5.	Gabriel H. Loh, Daniel A. Jimenez Reducing the Power and Complexity of Path-Based Neural Branch Prediction (pdf) In the 5th Workshop on Complexity Effective Design (WCED), pp. 1-8, June 5, 2005, Madison, WI, USA. (Held in conjunction with ISCA-32.)

6.	Gabriel H. Loh The Frankenpredictor: Stitching Together Nasty Bits of Other Predictors (pdf) In the 1st Championship Branch Prediction Contest (CBP1), pp. 1-4, Dec 6, 2004, Portland, OR, USA. (Held in conjunction with MICRO-37.)

7.	Gabriel H. Loh Width Prediction for Reducing Value Predictor Size and Power (pdf) In the 1st Value-Prediction Workshop (VPW1), pp. 86-93, June 7, 2003, San Diego, CA, USA. (Held in conjunction with ISCA-30.) (Also appears in an extended journal version.)

8.	Gabriel H. Loh, Rahul Sami, Daniel H. Friendly Memory Bypassing: Not Worth the Effort (pdf) In the Workshop on Duplicating, Deconstructing, and Debunking (WDDD), pp. 71-80, May 26, 2002, Anchorage, AK, USA. (Held in conjunction with ISCA-29.)


	Other

Gabriel H. Loh
Microarchitecture for Billion-Transistor VLSI Superscalar Processors (pdf)
PhD Thesis, Yale University, Dept. of Computer Science, New Haven, CT, USA, 255 pp., May 2002.