Research Projects Quick Links 3D Microarchitectures Multi-Core Resource Management High-Performance High-Efficiency μArchs 3D Microarchitectures See also: GT 3D Integration Research Over the last several years, a large amount of research has gone into making vertically intergrated chips feasible. By vertically stacking two or more silicon wafers, connected with a high-density, high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. While there has been a lot of fundamental research in showing that 3D chips can in fact be built, there has not been very much research activity in figuring out what should be done with this new technology. In particular, we are interested in answering the question: what should a high-performance microprocessor look like in 3D? Three-dimensional intergrated circuits allows a time-warp for Moore's Law. By stacking two wafers, the transistor density can be doubled using today's technology. This provides a left-shift of the Moore's Law curve by 18 months. A stack of four wafers provides a 3-year shift. Unfortunately, this shift applies to many of the Moore's Law "corrolaries". For example, every doubling of transistor density also comes with a doubling of power density. While the cost of 3D ICs is far less than the cost of constructing a next-generation fab, it does add processing steps and expense. We also do not receive the traditional speed-boost that accompanies each new process generation: we receive twice the transistor, but they are today's transistors, not the transistors available 18 months from now. Besides transistor density, the other major and potentially revolutionary benefit of 3D integration is the possibility of routing in the third dimension. Many people in both industry and academia have been worried about the rapid growth of RC delays relative to transistor speeds. 3D provides a way to reduce the long global routes by vertically stacking functional unit blocks (FUBs), or even folding individual FUBs. It is our hypothesis that blinding shoe-horning conventional planar microarchitectures into a 3D-process will fail to realize the full potential of this new technology. Our research goal is to understand the new tradeoffs in a 3D world, and use that knowledge to find the ultimate 3D microarchitecture. Funding for this project has been generously provided by the Focus Center for Circuit & Systems Solutions, and the NSF. 3D Microarchitecture/Circuit Papers: (PDF pre-prints available on the Publications page.) 1. Gabriel H. Loh, 3D-Stacked Memory Architectures for Multi-Core Processors, 35th ACM International Symposium on Computer Architecture (ISCA), June 2008 2. Gabriel H. Loh, A Modular 3D Processor for Flexible Product Design and Technology Migration, ACM International Conference on Computing Frontiers (CF), May 2008