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Milos Prvulovic
Associate Professor Teaching |
Computer architecture with emphasis on architectural support for programmability and programmer productivity, many-core performance, and security.
Ioannis Doudalis and Milos Prvulovic,
Euripus: A Flexible Unified Hardware Memory Checkpointing
Accelerator for Bidirectional-Debugging and Reliability,
Proceedings of the 39th IEEE/ACM International Symposium on Computer Architecture (ISCA),
June 2012.
(PDF)
Ioannis Doudalis, James Clause, Guru Venkataramani,
Milos Prvulovic, and Alessandro Orso,
Effective and Efficient Memory Protection
Using Dynamic Tainting,,
IEEE Transactions on Computers (TC),
Pages 87-100, Vol. 61, Issue 1, January 2012.
(PDF)
Ioannis Doudalis and Milos Prvulovic,
HARE++: Hardware Assisted Reverse Execution Revisited,
Workshop on Runtime Environments/Systems, Layering, and
Virtualized Environments (RESoLVE),
March 2011.
(PDF)
Ioannis Doudalis and Milos Prvulovic,
HARE: Hardware Assisted Reverse Execution,
Proceedings of the 16th IEEE International Symposium on
High-Performance Computer Architecture (HPCA),
January 2010. (PDF)
Guru Venkataramani, Christopher J. Hughes, Sanjeev Kumar, and Milos Prvulovic,
Coherence Miss Classification For Performance Debugging in Multi-Core Processors,
Thirteenth Workshop on Interaction between Compilers and Computer Architecture (Interact-13),
held in conjunction with HPCA'09,
February 2009. (PDF)
Guru Venkataramani, Ioannis Doudalis, Yan Solihin, and Milos Prvulovic,
FlexiTaint: A Programmable Accelerator for Dynamic Taint Propagation,
Proceedings of the 14th IEEE International Symposium on
High-Performance Computer Architecture (HPCA), pages 173-184,
February 2008. (PDF)
Brian Rogers, Chenyu Yan, Sidhartha Chhabra, Milos Prvulovic, Yan Solihin,
Single-Level Integrity and Confidentiality Protection for
Distributed Shared Memory Multiprocessors,
Proceedings of the 14th IEEE International Symposium on
High-Performance Computer Architecture (HPCA), pages 161-172,
February 2008.
Samantika Subramaniam, Milos Prvulovic, and Gabriel H. Loh,
PEEP: Exploiting Predictability of Memory Dependences in SMT Processors,
Proceedings of the 14th IEEE International Symposium on
High-Performance Computer Architecture (HPCA), pages 137-148,
February 2008. (PDF)
Brian Rogers, Siddhartha Chhabra, Yan Solihin, and Milos Prvulovic,
Using Address Independent Seed Encryption and Bonsai Merkle Trees
to Make Secure Processors OS- and Performance-Friendly,
Proceedings of the 40th Annual IEEE/ACM Symposium on Microarchitecture (MICRO),
December 2007. (PDF)
James Clause, Ioannis Doudalis, Alessandro Orso, and Milos Prvulovic,
Effective Memory Protection Using Dynamic Tainting,
Proceedings of the 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE),
November 2007.(PDF)
Guru Venkataramani, Brandyn Roemer, Yan Solihin, and Milos Prvulovic,
MemTracker: Efficient and Programmable Support for
Memory Access Monitoring and Debugging,
Proceedings of the 13th IEEE International Symposium on
High-Performance Computer Architecture (HPCA-13), pages 273-284,
February 2007. (PDF)
Mazen Kharbutli, Xiaowei Jiang, Yan Solihin, Guru Venkataramani, and Milos Prvulovic,
Comprehensively and Efficiently Protecting the Heap,
Proceedings of the 12th International Conference on
Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 207-218,
October 2006. (PDF)
Jianli Shen, Guru Venkataramani, and Milos Prvulovic,
Tradeoffs in Fine-Grained Heap Memory Protection,
First Workshop on Architectural and Systems Support for
Improving Software Dependability (ASID)
pages 52--57, October 2006.
Brian Rogers, Milos Prvulovic, and Yan Solihin,
Efficient Data Protection for Distributed Shared Memory Multiprocessors,
Proceedings of the 15th International Conference on
Parallel Architectures and Compilation Techniques (PACT),
September 2006. (PDF)
Chenyu Yan, Brian Rogers, Daniel Englender, Yan Solihin, and Milos Prvulovic,
Improving Cost, Performance, and Security
of Memory Encryption and Authentication,
Proceedings of the 33rd IEEE/ACM International Symposium on
Computer Architecture (ISCA), pages 179-190,
June 2006. (PDF)
Milos Prvulovic,
CORD: Cost-effective (and nearly overhead-free) Order
Recording and Data race detection,
Proceedings of the 12th IEEE International Symposium on
High-Performance Computer Architecture (HPCA-12), pages 236-247,
February 2006. (PDF)
Rithin Shetty, Mazen Kharbutli, Yan Solihin, and Milos Prvulovic,
HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection,
IBM Journal of Research and Development,
pages 261-275, Vol 50, Number 2/3, February 2006.
Maria Jesus Garzaran, Milos Prvulovic, Jose Maria Llaberia,
Victor Vinals, Lawrence Rauchwerger, and Josep Torrellas,
Tradeoffs in Buffering Speculative Memory State for
Thread-Level Speculation in Multiprocessors,
ACM Transactions on Architecture and Code Optimization (TACO),
pages 247-279, Vol 2, Issue 3, September 2005.
Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, and Milos Prvulovic,
Synonymous address compaction for energy reduction in data TLB,
Proceedings of the 2005 IEEE International Symposium on Low
Power Electronics and Design (ISLPED),
pages 357-362, August 2005.
Brian Rogers, Yan Solihin, Milos Prvulovic,
Memory Predecryption: Hiding the Latency Overhead of Memory Encryption,
ACM SIGARCH Computer Architecture News, special issue on
the Workshop on Architectural Support for Security and
Anti-virus (WASSA),
pages 27-33, Vol. 33, Issue 1, March 2005.
Rithin Shetty, Mazen Kharbutli, Yan Solihin, and Milos Prvulovic,
HeapMon: a Low Overhead, Automatic, and Programmable
Memory Bug Detector,
Proceedings of the First IBM PAC2 Conference,
October 2003. (PDF)
M. Garzaran, M. Prvulovic, V. Vinals, J. Llaberia, L. Rauchwerger, J. Torrellas,
Using Software Logging to Support Multi-Version Buffering in Thread-Level
Speculation,
Proceedings of the 2003 International Conference on Parallel Architectures and
Compilation Techniques (PACT), September 2003.
M. Prvulovic,
Architectural Support for Reliable Parallel Computing,
University of Illinois at Urbana-Champaign,
Department of Computer Science Technical Report #UIUCDCS-R-2003-2365,
July 2003.
M. Prvulovic, J. Torrellas,
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data
Races in Multithreaded Codes,
Proceedings of the 30th IEEE/ACM Annual International
Symposium on Computer Architecture (ISCA), June 2003.
(PDF)
M. Garzaran, M. Prvulovic, J. Llaberia, V. Vinals,
L. Rauchwerger, J. Torrellas,
Tradeoffs in Buffering Multi-Version Memory State for Speculative
Thread-Level Parallelization in Multiprocessors,
Proceedings of the Ninth International Symposium on High
Performance Computer Architecture (HPCA), February 2003.
(PDF)
M. Garzaran, M. Prvulovic, J. Llaberia, V. Vinals,
L. Rauchwerger, J. Torrellas,
Software Logging under Speculative Parallelization,
Second Workshop on Memory Performance Issues in conjunction
with ISCA-29, June 2001.
Extended version appears in
"High Performance Memory Systems",
edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda,
and J. Torrellas, Springer-Verlag, 2003.
J. Martínez, J. Renau, M. C. Huang, M. Prvulovic, J. Torrellas,
Cherry: Checkpointed Early Resurce Recycling in Out-of-order
Microprocessors,
Proceedings of the 35th Annual IEEE/ACM International Symposium on
Microarchitecture (MICRO), November 2002.
(PDF)
M. Prvulovic, Z. Zhang, J. Torrellas,
ReVive: Cost-Effective Architectural Support for Rollback
Recovery in Shared-Memory Multiprocessors,
Proceedings of the 29th IEEE/ACM Annual International Symposium on
Computer Architecture (ISCA), May 2002.
(PDF)
F. Dang, M.J. Garzaran, M. Prvulovic, Y. Zhang,
A. Jula, H. Yu, N. Amato, L. Rauchwerger, J. Torrellas,
SmartApps: An Application Centric Approach to High
Performance Computing: Compiler-Assisted Software and
Hardware Support for Reduction Operations,
Proceedings of the 2002 IEEE International Parallel and
Distributed Processing Symposium (IPDPS),
pages 172--181, April 2002.
M. Garzaran, M. Prvulovic, A. Jula, H. Yu,
Y. Zhang, L. Rauchwerger, J. Torrellas,
Architectural Support for Parallel Reductions in
Scalable Shared-Memory Multiprocessors,
Proceedings of the 2001 International Conference on
Parallel Architectures and Compilation Techniques
(PACT), September 2001.
(PDF)
M. Prvulovic, M. Garzaran, , L. Rauchwerger, J. Torrellas,
Removing Architectural Bottlenecks to the Scalability
of Speculative Parallelization,
Proceedings of the 28th IEEE/ACM Annual International Symposium
on Computer Architecture (ISCA), July 2001.
(PDF)
S. Roy, R. Kumar, M. Prvulovic,
Memory System Performance with Compressed Memory,
Proceedings of the International Parallel and Distributed
Processing Symposium (IPDPS), April 2001.
M. Prvulovic, D. Marinov, Z. Dimitrijevic, V. Milutinovic,
Split Temporal/Spatial Cache: A Survey and Reevaluation
of Performance,
in Newsletter of Technical Committee on Computer Architecture,
IEEE Computer Society, July 1999.
M. Prvulovic, D. Marinov, Z. Dimitrijevic, V. Milutinovic,
The Split Spatial/Non-Spatial Cache: A Performance and
Complexity Evaluation,
in Newsletter of Technical Committee on Computer Architecture,
IEEE Computer Society, July 1999.
M. Prvulovic, D. Marinov, V. Milutinovic,
Performance Evaluation of Split Temporal/Spatial Caches:
Paving the Way to New Solutions,
Proceedings of the Workshop on Performance Analysis and its
Impact to Design (PAID) in conjunction with ISCA-25,
June 1998.
(PDF)
J. Protic, M. Prvulovic, D. Ristanovic,
The Effects of User Behavior and Internet Provider Policy
on the Accessibility of SezamPro Online System,
23rd EUROMICRO Conference '97 New Frontiers of Information
Technology - Short Contributions, September 1997.
(PDF)