--------------------------------------------------------------------- CS 8803 AIC Paper Review Form --------------------------------------------------------------------- Reviewer's Name and affiliation Wouldn't you like to know :) --------------------------------------------------------------------- Paper Title: Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling --------------------------------------------------------------------- Overall evaluation of work and contribution [1-10] : 7 Scale Definition: 10=Excellent work and a major contribution 7=Good solid work of some importance 5=Solid work but marginal contribution 3=Marginal work and very minor contribution 1=Very questionable work and contribution ---------------------------------------------------------------------- Originality / Novelty [1-10] : 7 Scale Definition: 10=Trailblazing 7=A pioneering piece of work 5=One step ahead of the pack 3=Yet another paper about ... 1=Ancient Egyptians did this first ---------------------------------------------------------------------- Relevance to the class [1-10] : 10 Scale Definition: 10=Right on target 8=Definitely relevant 4=Close enough 3=Not really appropriate for this class 1=Definitely inappropriate for this class --------------------------------------------------------------------- Writing quality, Readability and Organization Your Rating [1-10] : 10 Scale Definition: 10=Very good 7=Basically well written 5=Readable 3=Needs considerable work 1=Completely incomprehensible --------------------------------------------------------------------- Overall recommendation [1-10] : 7 Scale Definition: 10=Definitely accept (very high quality) 7=Accept (good quality) 5=Accept if room (marginal quality) 3=Weak reject 1=Accept only over my dead body --------------------------------------------------------------------- Summary [Please summarize the paper in your own words and very few sentences.] This study deals with design trade-off in Multi-core architecture, especially focused on the interconnections. The overall performance is found to be affected not only by interconnection latency or bandwidth, but also by area of interconnections which can be used for bigger cache or another core otherwise. Power consumption in interconnections is also found to be very important factor in future multi-core architecture. Thus, it is highly necessary to co-design core, cache and interconnection. ---------------------------------------------------------------------- What is the strength of the paper? (1-3 sentences): This paper addresses many design issues simultaneously that the architect should consider, while other studies are just focused on only one issue such as performance or power consumption. Another good point is that alternative design strategies are also well addressed such as using remaining area with bigger caches when we use a bus with narrower bandwidth. --------------------------------------------------------------------- What is the weakness of the paper? (1-3 sentences): Simulation details are not mentioned. Heat dissipation problem is not mentioned, which is known to be very dependent on the wire floor-planning. --------------------------------------------------------------------- Questions you would like the authors to address before you make a final decision whether to accept this paper to the conference: How did you model bus arbitration latency, network access latency, etc.? I guess they must not be uniform. --------------------------------------------------------------------- Comments (will be returned to the author(s)) [Comment on strengths and weaknesses of the paper; in particular note any ways in which the paper could be improved.] It would be great if you also consider the heat dissipation problem, which is known to be related with wires, especially buses. --------------------------------------------------------------------- Confidential Comments (will NOT be seen by the author(s)) ---------------------------------------------------------------------