Santosh Pande Associate Professor College of Computing Georgia Institute of Technology College of Computing, Rm. 253 801 Atlantic Drive Atlanta, GA 30332-0280, USA Voice: (+1) (404) 385 2169 Fax: (+1) (404) 385 2295 E-mail: santosh at cc.gatech.edu

Biography

Santosh Pande's primary interest is in investigating static and dynamic compiler optimizations on evolving architectures. His research philosophy involves tackling practical problems which are relevant and important to the current issues in systems research and propose foundational solutions to them for good impact. Currently, his research is focussed on developing compiler optimizations for embedded and configurable systems to improve code size, efficiency and power consumption. His work in this area has resulted in several techniques for efficient compilation given limited memory sizes, limited addressing modes and data paths on embedded processors. He has also developed unified framework for mapping loops on configurable processors combining issues of parallelism, data re-use and reconfiguration overheads for modern processors such as Xilinx 6200 and Virtex series. He has also done work on efficient type inferencing and MOD analysis for OO languages and Java bytecode compilation. In addition to this, in past, he has done work on loop and task parallelism for distributed memory systems. He has published over 40 papers in journals and conferences which include ACM Programming Language Design and Implementation (PLDI), IEEE Real Time Systems Symposium (RTSS) and Journal of Parallel and Distributed Computing (JPDC) and IEEE Transactions on Parallel and Distributed Systems (TPDS). He has also done extensive compiler development and is a part of SUIF collaborative program amongst universities. He has also managed and delivered large scale software projects to the funding agencies such as DARPA.

He served as a co-guest editor for the special issue of Journal of Parallel and Distributed Systems on `Compilation Techniques for Distributed Memory Systems' published in December '96 and also for the special issue of the Parallel Processing Letters journal on `Challenges in Compiler Optimizations for Scalable Parallel Systems' published in December '97. He has also served on program committees of many conferences. Currently he is co-chairing ACM LCTES '01 to be held in conjunction with PLDI '01. He recently served on the program committee of PLDI '01. He served as an IEEE Distinguished Visitor for the period of 1996-2000. His research is primarily supported by the NSF and DARPA.


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• PC Member, 2004 International Conference on Parallel Processing (ICPP).
• PC Member, 2004 Code Generation and Optimization Conference (CGO).
• Vice-Chair, 2003 International Conference on Parallel Processing (ICPP)
• Program Committee Member, 2002 IEEE High Performance Computer Architecture Conference (HPCA 2002)
• Program Committee Member, 2002 International Conferences on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2002)
• Member of Steering Committee, ACM SIGPLAN Conference on Languages, Compilers and Tools for Embedded Systems (LCTES).
• Program Committee Member, 2002 ACM SIGPLAN Conference on Languages, Compilers and Tools for Embedded Systems (LCTES), Berlin, Germany.
• Co-Chair, 2001 IEEE Workshop on Embedded Systems, December 17th 2001, Hyderabad, India.
• Co-Chair, 2001 ACM Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES 2001)
• Program Committee Member, 2001 ACM Programming Language Design and Implementation Conference (PLDI 2001)
• Member of Program Committee, International Conference on Parallel Processing (Languages and Compilers area), September 2000, Toronto, Canada.
• Member of Program Committee, 1998 International Conference on Parallel Processing (Languages and Compilers Area)
• Mini-track co-ordinator, 'Compiling for Distributed Embedded Systems' 1998 Hawaii International Conference on System Sciences, Big Island, Hawaii, Jan. 6-10, 1998.
• Member of Program Committee, Fifth International Conference on Advanced Computing (ADCOMP '97), Madras, India, December 15-17, 1997 (in co-operation with IEEE Computer Society).
• Member of Program Committee, 1997 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA '97), Las Vegas, June 30 'EJuly 2 1997 (sponsored by DOE and EPA).
• Member of Program Committee of 8th International Conference on Computing and Information, June 1996, University of Waterloo, Canada.
• Member of Program Committee, 8th IEEE Symposium on Parallel and Distributed Systems, New Orleans, 1996.
• Member of Program Committee of 7th International Conference on Computing and Information, May 1995, Peterborough, Canada.

• Workshop co-ordinator (along with J. Ramanujam, LSU and Y. Robert, ENS-Lyon), 'Challenges in Compiling for Scalable Parallel Architectures' 8th IEEE Symposium on Parallel and Distributed Systems, New Orleans, Louisiana, 24th October, 1996.
• Workshop co-ordinator, 'Compiler Optimizations for Distributed Memory Systems' 7th IEEE Symposium on Parallel and Distributed Systems, San Antonio, Texas, 25th Oct., 1995.

• Recently Taught Courses