cc.gatech.eduBefore coming here, I graduated from the University of North Carolina at Chapel Hill (UNC) with an MS degree in Computer Science in May, 2008 and with a B.Tech degree from the Department of Computer Science & Engineering at Indian Institute of Technology Madras (IIT M), India in July 2006.
Research
I am currently working with Dr. Karsten Schwan in the systems research group. I am a member of Center for Experimental Research in Computer Systems (CERCS). My research interests include operating system, virtualization, and distributed systems with a focus on energy efficiency in my current work.
Operating System Support for Asymmetric Multicore Platforms
Currently working on resource management techniques to support novel architectural solutions involving heterogeneous multicores consisting of cores with different performance and power characteristics, with the aim of maximizing energy-efficiency for large-scale datacenters and handheld mobile devices.
Previous Work
Energy Conservation in Asynchronous Systems using Self-Adaptive Fine-Grain Voltage Scaling
Energy Conservation in Asynchronous Systems using Self-Adaptive Fine-Grain Voltage Scaling
During my MS at UNC Chapel Hill, I worked with Dr. Montek Singh on energy conservation in asynchronous systems using self-adaptive fine-grain voltage scaling (my MS thesis).
Delay and Peak-Power Minimization for On-chip Buses using Temporal Redundancy
In my undergraduation, I worked with Dr. V. Kamakoti on delay and peak-power minimization for on-chip buses using temporal redundancy.
Publications
- HeteroMates: Providing high dynamic power range on client devices using heterogeneous core groups
Vishal Gupta, Paul Brett, David Koufaty, Dheeraj Reddy, Scott Hahn, Karsten Schwan, and Ganapati Srinivasa. IEEE International Green Computing Conference, (IGCC), 2012 (To appear) - The Forgotten 'Uncore': On the Energy-efficiency of Heterogeneous Cores
Vishal Gupta, Paul Brett, David Koufaty, Dheeraj Reddy, Scott Hahn, Karsten Schwan, and Ganapati Srinivasa. USENIX ATC 2012 Short Paper (To appear) - An Analysis of Power Reduction in Datacenters using Heterogeneous Chip Multiprocessors
Vishal Gupta, Ripal Nathuji, and Karsten Schwan SIGMETRICS PER March, 2012 (Invited Paper) - Extending the dynamic power range of client devices using heterogeneous multicore processors
Vishal Gupta, Paul Brett, David Koufaty, Dheeraj Reddy, Scott Hahn, Karsten Schwan, and Ganapati Srinivasa. SHAW 2012 (To appear) - Evaluating Scalability Bottlenecks in Multi-threaded Applications on a Many-core Platform
Vishal Gupta, Hyesoon Kim, and Karsten Schwan Tech. Report GIT-CERCS-12-03 [pdf] - An Analysis of Power Reduction in Datacenters using Heterogeneous Chip Multiprocessors
Vishal Gupta, Ripal Nathuji, and Karsten Schwan ACM GreenMetrics 2011, San Jose, CA [pdf] - Analyzing Performance Asymmetric Multicore Processors for Latency Sensitive Datacenter Applications
Vishal Gupta, Ripal Nathuji, Usenix HotPower 2010, Vancouver, Canada [pdf] - Performance Estimation and Slack Matching for Pipelined Asynchronous Architectures with Choice
Gennette Gill, Vishal Gupta, Montek Singh
International Conference on Computer-Aided Design, 2008 (ICCAD'08). [pdf] - Robust Performance Estimation and Slack Matching for Pipelined Asynchronous Architectures with Choice
Gennette Gill, Vishal Gupta, Montek Singh
International Workshop on Logic & Synthesis (IWLS), California, USA, June 2008. [pdf] - Temporal Redundancy Based Temporal Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. K. Najeeb, Vishal Gupta, V. Kamakoti, and Madhu Mutyam
Journal of Low Power Electronics (JOLPE) 2006 [pdf] - Delay and Energy Minimization for On-Chip Buses using Temporal Redundancy
K. Najeeb, Vishal Gupta, V. Kamakoti, and Madhu Mutyam
Great Lakes Symposium on VLSI (GLSVLSI'06) [pdf]
Posters
- HeteroMates: Providing high dynamic power range on client devices using heterogeneous core groups
USENIX ATC 2012 Poster Session [pdf] - Using heterogeneous cores to provide a high dynamic power range on over-provisioned processors
First Dark Silicon Workshop (with ISCA) 2012 (Presentation abstract) [pdf] - Extending the dynamic power range of client devices using heterogeneous multicore processors
Intel Embedded Research and Education Summit, Feb 2012, Chandler, AZ [pdf] - Messy: A Shared-Memory Library for Intel Single-chip Cloud Computer (SCC)
Intel Manycore Applications Research Community (MARC) SCC Symposium, April 2011, Santa Clara, CA [pdf]
Academics
Resume [pdf]
You can also check my public profile at LinkedIn.Grade Summary
- Ph.D. transcript (Georgia Tech) [pdf]
- M.S. transcript (UNC-CH) [pdf]
- B.Tech transcript (IIT Madras) [pdf]
Work Experience
- Intel Labs, Hillsboro, OR (June 2011-Jan 2012) Worked with the System Architecture Labs on techniques to extend the dynamic power range of client devices using heterogeneous multicore processors. Specifically, this work aims in using a mix of heterogeneous cores to provide both high-performance and low-power modes while maintaining energy-efficiency.
- Microsoft Research, Redmond, WA (May-July 2010) Performed an opportunity analysis of heterogeneous chip multiprocessors for the datacenter applications. Using analytical models, this work presents an analysis of achievable energy savings of heterogeneous multicore processors over homogeneous processors for area equivalent configurations.
- Google, Mountain View, CA (Jun-Aug 2009) Worked on non-temporal cache prefetching techniques to prevent CPU cache pollution. Using reuse distance as an input, this work modifies an application binary to insert non-temporal access prefetch instructions at appropriate positions to not cache data with no temporal locality.
- IBM India Research Lab (IRL), New Delhi, India (May-July 2008) Worked on parallelizing a sequential SAT solver named Minisat on Blue-Gene. It was designed to be scalable using a state machine based coordination mechanism and a master-slave architecture.
- Yahoo!, Sunnyvale, CA (May-Aug 2007) Developed an API which enables users to categorize data by applying keyword tags and perform a search using these tags. Also, implemented a simple web-based front-end to use this API.
- Open-Silicon, Bangalore, India (May-Jun 2005) Performed standard cell library characterization for digital gates, latches, and flip-flops using Spice.
- RISE Lab, IIT Madras, India (Internship: sponsored by Intel India) (Jun-Aug 2004) Testing of decoder unit for a behavioral model simulator of Intel x86 core.
Personal
I like to read, cook, and listen to music in my leisure time. Some useful applications:
- Multi-platform file synchronizer: Dropbox
- Bibliography Manager: Mendeley
- Python library for graphs: Matplotlib
- Vector Graphics: Inkscape
Contact
The easiest and the fastest way to reach me is to e-mail me.#3206 (CERCS Lab)
Klaus Advanced Computing Building
Georgia Institute of Technology
Atlanta, GA
Email: firstname AT cc DOT gatech DOT edu