Intel/GT Opportunity Scholar’s Program 2005-6

Research Agenda

Year: 2005

Mentor: Gerald Lopez

Scholars: Matthew Crowley, Mustafa Akbulut

Date Submitted: January 9, 2006

Research Area: The Impact of Induced Line Edge Roughness on Wires Using E-Beam Lithography

Proposed Research Tasks  

The scholars will be oriented and trained for clean room experience.  Their tasks will include assisting the graduate researcher with the fabrication and testing of wires fabricated using E-beam lithography with induced line edge roughness.  Wires will be fabricated in both copper and aluminum. 

Each scholar will be expected to operate at least two pieces of clean room equipment at the end of their experience.  They will understand the basics of clean room etiquette and have a better appreciation for the chip fabrication process.

Timeline:

November:  Clean Room orientation, Receive training on at least one machine

December:  Receive training on at least one machine

January:  Practice wire fabrication, perform uniformity measurements

February:  Complete fabrication, Begin to perform testing

March:  Complete testing and analysis

April:  Work on poster/paper