Publications

More Publications

In-RDBMS Hardware Acceleration of Advanced Analytics, Proceedings of the VLDB Endowment (PVLDB), August 2018.
2018

An End-to-End Solution to Accelerate Autonomous Control in Robotics, International Symposium on Computer Architecture (ISCA), June 2018
2018

Scale-out acceleration for machine learning, Proceedings of International Symposium on Microarchitecture (MICRO), October 2017.
2017

From High-Level Deep Neural Models to FPGAs, International Symposium on Microarchitecture (MICRO), October 2016.
2016

Towards Statistical Guarantees in Controlling Quality Tradeoffs in Approximate Acceleration, International Symposium on Computer Architecture (ISCA), June 2016.
2016

AXGAMES: Towards Crowdsourcing Quality Target Determination in Approximate Computing, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2016.
2016

TABLA: A Unified Template-based Framework for Accelerating Statistical Machine Learning, High-Performance Computer Architecture (HPCA), March 2016. Distinguished paper award
2016

Axilog: Abstractions for Approximate Hardware Design and Reuse. IEEE Micro Special Issue on Alternative Computing Designs & Technologies, October 2015.
2015

AxBench: A Multi-Platform Benchmark Suite for Approximate Computing, IEEE Design and Test, Special issue on Computing in the Dark Silicon Era, May 2016.
2015

Axilog: Language Support for Approximate Hardware Design. Design Automation and Test in Europe (DATE), March 2015.
2015

Industry Experience

 
 
 
 
 
May 2018 – August 2018
Redmond, WA

Research Intern

Microsoft Research

Worked on devising low-latency FPGA-based hardware accelerators for performing advanced analytics on semi-structured data.
 
 
 
 
 
May 2017 – August 2017
Westford, MA

Architecture Research Intern

Nvidia Research

Created compiler for a high-level user interface that can program specialized hardware design languages and increase the chips customer usability.
 
 
 
 
 
May 2016 – July 2016
Redmond, WA

Research Intern

Microsoft Research

Incorporated hardware compression techniques for better usage of memory for Deep Networks being accelerated by FPGAs.
 
 
 
 
 
May 2015 – August 2015
Cupertino, CA

Design Engineer

Apple Inc

Contributed to the simulation framework and performance evaluation of the architecture.
 
 
 
 
 
May 2013 – August 2013
Cupertino, CA

Logic Design Engineer

Apple Inc

Contributed to the design and implementation of architectural and design changes of the datapath contributing towards the area and power reduction.
 
 
 
 
 
May 2011 – July 2011
Birmingham, UK

Summer Intern

Aston University

Devised and created a wireless demonstration unit for a low cost optical fiber grating based sensor system.

Contact

  • divya[dot]mahajan[at]cc[dot]gatech[dot]edu
  • KACB 2336, 266 Ferst Drive, Atlanta, GA 30332-0765