CS7290 Advanced microarchitecture
Fall 2014
Instructor: Prof. Hyesoon Kim
Final Project
In your final project, you can choose either HDL programming or research project using a timing simulator.
You can do other projects. All project proposals should be discussed with the instructor on either Oct 31 (F) or Nov 3 (M) and
need to get an approval.
This can be a group project.
Research Project option
If you decide to do a research project, the work should be sufficient enough to write a workshop like paper.
Potential topics (but not limited) are as follows:
- Shared cache managements
- Better branch predictor algorithms
- Cache coherence optimization in CPU+GPUs
- GPU architecture optimization
- Non-traditional architectures
- Power/Energy efficient designs
You have to write a 6 ~ 8-page double column paper (IEEE style) as a final report and you will also have a 10-min presentation
in the last day of the class. Please see other
architecture conference papers as your reference.
HDL Programming option
You can extend your own CHDL design or you can use existing CHDL design and extend it.
MIPS core and HARP ISA cores are already existing.
The potential options as follows.
- Extend MIPS core to have a cache
- Multiple MIPS/HARP cores
- Supporting multi-level cache hierarchies
- Multiple caches and inter connection network
- Caches with coherence support
- Convert in-order cores to OOO cores for MIPS or HARP cores
You have to do a demo of your final implementation for the HDL programming option.
You also have to submit a short report to describe your work.
Schedule
- Proposal due: Oct 29 (W)
- Proposal feedback date: Oct 31 (F) or Nov (3)
- Progress report/demo due: Nov 21 (F)
- Final presentation & Demo Dec. 3 (W)
- Final report due: Dec. 5 (F)
What to submit
Proposal: about 800 words abstract to describe the topic. References and time line.
Progress report: IEEE format double column 3 page report. You must include related work section in the progress report.
Progress demo: Schedule a demo and show your progress.