CS7290 Advanced microarchitecture
Fall 2014
Instructor: Prof. Hyesoon Kim
Due: September 19 (Friday) 6 pm
Overview:
In this assignment, you extend your processor design (proj1.5)
to have a 3 stage pipelines: Fetch, Decode&Reg read, Execution.
The memory is accessed in the execution stage and the register values are updated in the execution stage as well.
We still do not support STW instruction in this assignment, so still
there is only one memory in the FE stage.
To keep the assignment simple, the pipeline is stalled whenever there is a data dependence
and a branch instruction.
The memory access takes only 1 cycle for this assignment.
You can do this project with another student in the class. A group project
What to submit
- Report:
- Screenshots of the waveforms. Please show whether you handle branch and data dependence correctly in the screenshots.
- You should clearly show whether the pipeline is correctly executed using the screen shot.
- all your source code.
please tar your all files and submit them as proj2.tar
Note: We only grade based on your report. The source code might be used to check
your implementation.
Grading policy:
- (25 points) Implementation of pipeline design
- (25 points) Handling data dependence and control dependence correctly
- (25 points) Report discussion.
Here is the testing assembly code