Micro-architecture/architecture
Addressing mode 
Pipelined design
ILD
Data dependencies
Control dependencies
Memory dependencies
Data Hazard/control hazard
ILP
RAW/WAR/WAW dependencies
Memory dependencies
Memory disambiguation
Data forwarding 
Scoreboard
Issue/read operands/write back 
Pipeline bubble 
Delayed branch 
Temporal locality/spatial locality 
Storage hierarchy
Cache 
Cache block/cache line
Cache replacement 
Write policy (write-back, write-through) 
Directed mapped cache 
Fully associative cache 
Set-associative cache 
Valid bit
Dirty bit 
Tag 
Write-allocate/no-write-allocate 
Compulsory, capacity, conflict cache misses 
AMAT 
SRAM/DRAM
Row buffer 
Destructive read 
Prefetcher
Register prefetch, cache prefetch 
Binding,non-biding prefetch 
Stream prefetcher 
Stride prefetcher
SMP 
Coarse MT, Fine MT 
SMT (Simultaneous Multithreading)/Hyperthreading 
TLB: Translation look-aside buffer
SISD/SIMD/MISD/MIMD
MMX
SSE
3DNow!
Loop unrolling 

Out of order execution
LRU replacement 
Pseudo LRU replacement 
Inclusion property
Merging write buffers
Flynn’s Taxonomy of parallel machines 
Centralized shared memory system
Virtual memory
Big  endian/Little endian 
Branch prediction
Branch prediction hint