March 20th, 2016Posted by Jeff

I am currently a Research Scientist at Georgia Tech working in the School of Computer Science in the College of Computing. My main research interests include investigating scheduling and data movement for accelerators like GPU and Xeon Phi and working to build better power models for HPC system components. In addition, I am currently working to help develop a new, collaborative research program focused on mapping bandwidth-intensive algorithms to 3D stacked memories like Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) as well as on performing near-memory computation on devices like FPGAs and GPUs.

My previous position at GT included working on advanced user support for the Keeneland project and investigating architecture-related research topics for Dr. Jeff Vetter's Future Technologies Group at Oak Ridge National Lab.

I defended my PhD in August 2013 in the area of computer architecture working under Dr. Sudhakar Yalamanchili. More information on this networks- and memory-related research can be found under the publications tab.

If you are interested in my current research or an up-to-date CV please check the links above for more information on my research or on how to contact me.