This assignment has four problems:
You will turn in your modified hw2_answers.txt file by the deadline specified on Sakai.
In this problem we consider a potential enhancement for the LC2200-16 datapath. The “PCINC” enhancement adds a separate incrementer for the program. The original datapath and a datapath that illustrates the enhancement are shown below:
Original LC2200-16 Datapath
Datapath with the PCINC Enhancement
A. [16 points] Give the states to control this datapath in order to execute the LC2200-16 ADDI instruction without the PCINC modification. Then do the same for a datapath with the PCINC modification. Start with instruction fetch.
Use this format and only list signals that are being asserted.
State1: DrPC, LdMAR, LdA
GoTo next state <--This may be a conditional expression and may be omitted if you want to just go to the following state.
B. [2 points] What is the CPI for ADDI with and without the PCINC enhancement?
C. [2 points] Assuming that the clock speed remains the same, what is the speedup for the ADDI instructions in the new datapath? Show your work.
A. [15 points] In the year 2020, both Intel and AMD decide to abandon their work on the x86, and instead develop processors based on the LC-2200-16 architecture. In order to build a faster processor than their competition, each manufacturer makes specific improvements to their implementation.
i. Using the chart below, calculate the speedup both gcc
and spice on each manufacturer's processor.
ii. Which processor will execute gcc the fastest?
iii. Which processor will execute spice the fastest?
Note: You do not need to understand how the enhancements work for this question. Simply use the average speedups given for each.
B. [10 points] The LC-2200-16 has no multiply instruction. Suppose we have the following two choices for performing multiplication:
What fraction of instructions must be multiplications in order to observe a 2X overall speedup of the hardware solution over the software emulation solution? For simplicity, assume that all LC-2200-16 instructions take the same number of clock cycles.
Hint: On this assignment and every other CS2200 homework, projects, and test, use your textbook's definition of speedup: execution time before improvement divided by execution time after improvement.
This question asks about the effect of interrupts on the execution time of a program.
Suppose you have a computer system with multiple peripherals (DISK, SOUND, and CLOCK) and the peripherals generate interrupts at predictable rates:
(0 is lowest)
|Arrival rate||Execution time
Assume the background task and all the interrupts initially fire at time 0 and that the interrupts then arrive periodically thereafter. E.g. the sound card interrupt arrives at time 0, 20mS, 40mS, etc.
A. [15 points] Draw a timing chart showing which task (the background task or the handler for one of the interrupts) is operating over the first 50mS of time. The chart should cover the first 50mS in 2mS intervals. E.g.:
Time BG DISK SOUND CLOCK
---- -- ---- ----- -----
B. [10 points] The background task requires 10 seconds of CPU time with no interrupts. However, the interrupt handlers require CPU time as well and will "steal" away some amount of time from the background task. How many seconds will it take to run the background task with the interrupt handlers running at the given rates?
C. [6 points] Interrupts often come with a "deadline", a specification of the maximum time from the time of the interrupt arrival to the time the handler *finishes* processing.
For each interrupt (DISK, SOUND, CLOCK), give the worst-case time to finish processing the handler.
For this section, we will introduce 3 "new" instructions that you may find useful:
A. [2 points]
When an interrupt is used to initiate a system call what is it called?
B. [12 points]
Below are the steps a typical interrupt handler will follow (assume interrupts are disabled upon entering the interrupt handler):
Sometimes, an interrupt handler will itself need to be interrupted. For this to happen, interrupts will need to be re-enabled during the execution of the handler. Identify the four steps (and where they belong in relation to the steps defined above) in order for this to occur properly.
C. [6 points]
Describe how are the processor registers are saved in stack during interrupt handling and why is it saved like that?
D. [4 points]
When an interrupt handler returns, it executes a special RETI instruction. This instruction is the atomic equivalent of what two other instructions?
End of CS 2200 Homework 2