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Georgia Tech Kiran Panesar

Hello, I work for Intel in Portland Oregon, in the Platform Architecture Labs.

I am a PhD from Georgia Tech, and my thesis research area was Parallel Simulation. My advisor was Professor Richard Fujimoto. For my thesis, I investigated performance and architectural issues for parallel discrete event simulations running on shared memory multiprocessors. I am interested in Computer Architecture, and Operating Systems .

Here is my resume.

Meet my wife, Ritu and our daughter Koodrut . Here are some more photos of Koodrut one, two, three, four, and five.

Links to other pages:
University of Roorkee my alma mater.
I went to University of Maryland for my masters in Computer Science.

India Club and SPICMACAY upcoming events, pointers to other www pages.
Chandigarh my home town and India .

Thesis Research:

Parallel and Distributed Simulation
My research is shared memory optimizations for high performance Time Warp: efficient message passing, buffer management, and fast continuous GVT calculations for real time applications.


Adaptive Flow Control in Time Warp With Richard Fujimoto, Eleventh Workshop on Parallel and Distributed Simulation. June 1997. Simple flow control mechanism to throttle overly optimistic execution.

Automatic Incremental State Saving With Darrin West, Tenth Workshop on Parallel and Distributed Simulation. May 1996. We use executable editing to insert state save calls in Time Warp executables.

Buffer Management in Shared Memory Time Warp Systems with Richard Fujimoto, 8th Workshop on Parallel and Distributed Simulation (PADS), June 1995. A high performance message passing system for shared memory multiprocessors is presented, by studing the interaction of memory management in Time Warp with caching and virtual memory.

Georgia Tech Time Warp (GTW Version 2.3) Programmer's Manual. with Richard Fujimoto and Samir Das. Technical Report. College of Computing, Georgia Institute of Technology, Atlanta, GA. July 1994.

GTW: A Time Warp System for Shared Memory Multiprocessors.Winter Simulation Conference (WSC), Dec 1994. Describes several shared memory optimizations for Time Warp.

PORTS: A Parallel, Optimistic, Real-Time Simulator. 8th Workshop on Parallel and Distributed Simulation (PADS '94). p. 24-31. Time Warp for real time systems.

Parallel Discrete Event Simulation on a Shared-Memory Multiprocessor with Richard Fujimoto and Maria Hybinette. Submitted for publication.

Contact Information:

Address: 6386 SW LOIS ST Hillsboro OR 97123

Other information available via finger .

Homepage last updated Aug 99