CS3220-X Processor Design
Spring 2015
|
Tentative Schedule
| Week |
Dates |
Topics |
Assignments |
| 1 |
1/5, 1/7 |
Overview & Digital Design
| |
| 2 |
1/12, 1/14 |
Combinational logic & Introduction to Verilog
| Assignment #1 (verilog) |
| 3 |
1/19, 1/21 |
Sequential logic
| No lecture on 1/19 |
| 4 |
1/26, 1/28 |
Introduction to FPGA
| Assignment #1 Due (1/28), Assignment #2 (FPGA Intro) |
| 5 |
2/2, 2/4 |
More combinational logic, arithmetic operations
| |
| 6 |
2/9, 2/11 |
line drawing, VGA, frame buffer
| Assignment #2 due (2/11), Assignment #3 (Line drawing) |
| 7 |
2/16, 2/18 |
Graphics operations(translations, rotations etc.)
| Assignment #3 due (2/16), Assignment #4 (line drawing) due 2/20 |
| 8 |
2/23, 2/25 |
Programmable GPU architectures
| Assignment #5 (trainagle rendering) due 3/1 |
| 9 |
3/2, 3/4 |
Programmable GPU architectures
| Assignment #6 (Functional Simulator processor) |
| 10 |
3/9, 3/11 |
Programmable pipeline
| Assignment #6 due (3/11) |
| 11 |
3/16, 3/18 |
Spring break
| |
| 12 |
3/23, 3/25 |
Pipelie design/Branch Predictor
| Assignment #7 5-stage processor |
| 13 |
3/30, 4/1 |
pipeline design/Branch predictor
| Assignment #7 Part I due (3/30), |
| 14 |
4/5, 4/8 |
pipeline design/multi-processors
| Assignment #7 5-stage pipeline Part II due (4/5) |
| 15 |
4/13, 4/15 |
cache coherence
| Assignment #8 Part I due (4/13) |
| 16 |
4/20, 4/22 |
OOO processors/SMT
| Assignment #8 due (4/19), optional assignment #9 (CPU+GPU demo 4/24) |
17 |
4/29 (2:50 - 5:40 pm) |
Optional Final Exam
| |
|