Professor Receives Third Test of Time Honor in Three Years
Professor Moinuddin Qureshi received the ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award at the International Symposium on Computer Architecture (ISCA 2026) on June 30.
Presented annually, the ISCA Influential Paper Award recognizes a standout paper from the ISCA Conference 18-22 years prior. Winning papers are those which have demonstrated “the most impact on the field (in terms of research, development, products or ideas) during the intervening years.”
The awarded paper, Adaptive Insertion Policies for High-Performance Caching, has been highly influential in cache replacement research. As a Ph.D. student at the University of Texas at Austin, Qureshi co-authored the paper with his advisor Yale Patt and collaborators from Intel, including Aamer Jaleel, Simon Steely, and Joel Emer.
“I’ve been working on memory systems for 20 years and if I had to pick one favorite paper, it would be this one,” Qureshi said. “Both because of the simplicity of the solution and for the impact it had.”
When the paper was published at ISCA 2007, on-chip cache sizes were growing but still managed almost exclusively by the Least Recently Used (LRU) replacement policy.
The paper showed that more than half of the lines in cache were discarded before they could be used under LRU policy and that this happened because the workloads being run were larger than the cache size. The team came up with a simple solution of modifying the “Insertion Policy”, such that the incoming lines were inserted at the LRU position instead of the MRU position, thus protecting the cache from thrashing patterns. The problem was that some workloads benefited from this policy while others were hurt by it.
Instead of applying one policy across the whole cache, their solution dynamically tested two small segments against each other, each running a different policy. Whichever policy had fewer cache misses was applied to the entire cache. They named this technique Set Dueling.
Qureshi clearly remembers the moment he knew this paper would be important. He was up late working on the project when he ran the final simulation with the solution.
“I was so excited that I just didn’t sleep that night. I knew that the solution would get incorporated and it would change how people think about caching. I could not wait to share the results with my collaborators” he said.
Set Dueling has since become a common technique for choosing between two competing policies when neither wins on all workloads. With close to 1,000 citations, the paper has greatly influenced research on cache optimization.
This recognition is Qureshi’s third test-of-time honor. In 2024, he received one at the IEEE/ACM International Symposium on Microarchitecture, for his work on Multi-core Cache Partitioning and in 2025, at the IEEE/IFIP International Conference on Dependable Systems and Networks, for his work on DRAM Reliability.
Qureshi said that his goal in working in computer architecture is to have an industry impact.
“It’s very gratifying to see that the ideas that we developed a decade or two decades ago are having an impact and being incorporated,” Qureshi said. “As a researcher, these are the best awards you can have because it serves as a validation that the work you’ve done is valuable to both industry and follow-up research.”
